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    Periodic Calibration For Communication Channels By Drift Tracking
    141.
    发明申请
    Periodic Calibration For Communication Channels By Drift Tracking 有权
    通过漂移跟踪进行通信通道的定期校准

    公开(公告)号：US20140133536A1

    公开(公告)日：2014-05-15

    申请号：US14145966

    申请日：2014-01-01

    Applicant: Rambus Inc.

    Inventor： Craig E. Hampel ,  Frederick A. Ware ,  Richard E. Perego

    IPC: H04B17/00

    CPC classification number: H04B17/11 ,  H04B17/00 ,  H04B17/21 ,  H04L7/0004 ,  H04L7/0016 ,  H04L7/0087 ,  H04L7/043 ,  H04L7/10 ,  H04L27/00

    Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

    Abstract translation: 提供执行第一校准序列的方法和系统，例如在系统初始化时，建立操作值，其利用旨在穷举的算法，并且不时地执行第二校准序列以测量 在参数中漂移，并根据测量的漂移更新操作值。 与第一校准序列相比，第二校准序列使用较少的通信信道资源。 在一个实施例中，用于操作值的测量和收敛的第一校准序列利用长校准模式，例如大于30字节的代码，或长度为2N-1位的伪随机比特序列，其中N等于或大于 而第二校准序列使用短校准模式，例如小于16字节的固定代码，例如短至2字节长。

    SELECTIVE REFRESH WITH SOFTWARE COMPONENTS
    143.
    发明申请
    SELECTIVE REFRESH WITH SOFTWARE COMPONENTS 审中-公开
    用软件组件进行选择性刷新

    公开(公告)号：US20140068172A1

    公开(公告)日：2014-03-06

    申请号：US13975873

    申请日：2013-08-26

    Applicant: Rambus Inc.

    Inventor： Hongzhong Zheng ,  James Tringali ,  Frederick A. Ware

    IPC: G11C11/406

    CPC classification number: G11C11/406 ,  G06F12/08 ,  G06F12/1009 ,  Y02D10/13

    Abstract: A method of refreshing a memory is disclosed. The method includes accessing from active memory an active memory map. The active memory map is generated by software and identifies addresses corresponding to the active memory and associated refresh criteria for the addresses. The refresh criteria are evaluated for a portion of the active memory, and an operation initiated to refresh a portion of the active memory is based on the refresh criteria.

    Abstract translation: 公开了一种刷新存储器的方法。 该方法包括从活动存储器访问活动存储器映射。 活动存储器映射由软件产生，并且识别与活动存储器相对应的地址和用于地址的相关联的刷新标准。 针对活动存储器的一部分评估刷新标准，并且基于刷新准则启动刷新活动存储器的一部分的操作。

    Reducing Memory Refresh Exit Time
    144.
    发明申请
    Reducing Memory Refresh Exit Time 有权
    减少内存刷新退出时间

    公开(公告)号：US20140016423A1

    公开(公告)日：2014-01-16

    申请号：US13938130

    申请日：2013-07-09

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent Haukness ,  Ian P. Shaeffer ,  James E. Harris

    IPC: G11C7/00

    CPC classification number: G11C7/00 ,  G11C7/1009 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40622

    Abstract: Components of a memory system, such as a memory controller and a memory device, that reduce delay in exiting self-refresh mode by controlling the refresh timing of the memory device. The memory device includes a memory core. An interface circuit of the memory device receives an external refresh signal indicating an intermittent refresh event. A refresh circuit of the memory device generates an internal refresh signal indicating an internal refresh event of the memory device. A refresh control circuit of the memory device performs a refresh operation on a portion of the memory core responsive to the internal refresh event, at a time relative to the intermittent refresh event indicated by the external refresh signal.

    Abstract translation: 诸如存储器控制器和存储器设备的存储器系统的组件通过控制存储器件的刷新定时来减少退出自刷新模式的延迟。 存储器件包括存储器核。 存储装置的接口电路接收指示间歇刷新事件的外部刷新信号。 存储器件的刷新电路产生指示存储器件的内部刷新事件的内部刷新信号。 存储器件的刷新控制电路响应于内部刷新事件，在相对于由外部刷新信号指示的间歇刷新事件的时间，对存储器核心的一部分执行刷新操作。

    MEMORY MODULE HAVING A WRITE-TIMING CALIBRATION MODE
    146.
    发明申请
    MEMORY MODULE HAVING A WRITE-TIMING CALIBRATION MODE 有权
    具有写入时间校准模式的存储模块

    公开(公告)号：US20130262757A1

    公开(公告)日：2013-10-03

    申请号：US13890801

    申请日：2013-05-09

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware

    IPC: G11C7/10

    CPC classification number: G11C11/4076 ,  G06F1/10 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  G11C11/409 ,  G11C2207/2254

    Abstract: In memory module populated by memory components having a write-timing calibration mode, control information that specifies a write operation is received via an address/control signal path and write data corresponding to the write operation is received via a data signal path. Each memory component receives multiple delayed versions of a timing signal used to indicate that the write data is valid, and outputs signals corresponding to the multiple delayed versions of the timing signal to enable determination, in a memory controller, of a delay interval between outputting the control information on the address/control signal path and outputting the write data on the data signal path.

    Abstract translation: 在由具有写定时校准模式的存储器组件填充的存储器模块中，经由地址/控制信号路径接收指定写入操作的控制信息，并经由数据信号路径接收与写操作对应的写数据。 每个存储器组件接收用于指示写入数据有效的定时信号的多个延迟版本，并且输出与定时信号的多个延迟版本对应的信号，以使得能够在存储器控制器中确定输出 对地址/控制信号路径进行控制信息，并在数据信号路径上输出写入数据。

    MEMORY COMPONENT WITH ADJUSTABLE CORE-TO-INTERFACE DATA RATE RATIO
    148.
    发明申请
    MEMORY COMPONENT WITH ADJUSTABLE CORE-TO-INTERFACE DATA RATE RATIO 有权

    公开(公告)号：US20250054525A1

    公开(公告)日：2025-02-13

    申请号：US18809247

    申请日：2024-08-19

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely K. Tsern

    IPC: G11C7/10

    Abstract: A memory component includes a memory bank comprising a plurality of storage cells and a data interface block configured to transfer data between the memory component and a component external to the memory component. The memory component further includes a plurality of column interface buses coupled between the memory bank and the data interface block, wherein a first column interface bus of the plurality of column interface buses is configured to transfer data between a first storage cell of the plurality of storage cells and the data interface block during a first access operation and wherein a second column interface bus of the plurality of column interface buses is configured to transfer the data between the first storage cell and the data interface block during a second access operation.

    Protocol for refresh between a memory controller and a memory device
    150.
    发明授权
    Protocol for refresh between a memory controller and a memory device 有权

    公开(公告)号：US12211540B2

    公开(公告)日：2025-01-28

    申请号：US18399096

    申请日：2023-12-28

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent Haukness

    IPC: G06F12/00 ,  G06F13/16 ,  G11C11/406

    Abstract: The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

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