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    Low power edge and data sampling
    141.
    发明授权
    Low power edge and data sampling 有权

    公开(公告)号：US12200096B2

    公开(公告)日：2025-01-14

    申请号：US18237375

    申请日：2023-08-23

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe

    IPC: H04L7/033 ,  H04L7/00

    Abstract: An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.

    Using a stuttered clock signal to reduce self-induced voltage noise
    145.
    发明授权
    Using a stuttered clock signal to reduce self-induced voltage noise 有权

    公开(公告)号：US11181941B2

    公开(公告)日：2021-11-23

    申请号：US16546687

    申请日：2019-08-21

    Applicant: Rambus Inc.

    Inventor： Brian S. Leibowitz ,  Jared L. Zerbe

    IPC: G06F1/12 ,  G06F1/08 ,  G06F1/3237

    Abstract: The disclosed embodiments relate to a technique that uses a modified timing signal to reduce self-induced voltage noise in a synchronous system. During a transient period associated with a deterministic event in the synchronous system, the technique uses a modified timing signal generated based on a normal timing signal as a timing signal for the synchronous system. Outside of the transient period, the technique uses the normal timing as the timing signal for the synchronous system. In some embodiments, the modified timing signal is generated by skipping a pattern of clock transitions in the normal timing signal.

    Selectable-tap Equalizer
    146.
    发明申请
    Selectable-tap Equalizer 有权

    公开(公告)号：US20210067384A1

    公开(公告)日：2021-03-04

    申请号：US17024843

    申请日：2020-09-18

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Vladimir M. Stojanovic ,  Fred F. Chen

    IPC: H04L25/03 ,  H04B1/10 ,  H04L7/00 ,  H04L7/033

    Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

    Clock Generation for Timing Communications with Ranks of Memory Devices
    147.
    发明申请
    Clock Generation for Timing Communications with Ranks of Memory Devices 有权

    公开(公告)号：US20210049118A1

    公开(公告)日：2021-02-18

    申请号：US16921061

    申请日：2020-07-06

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

    IPC: G06F13/16 ,  G06F1/10 ,  G11C7/22 ,  G06F1/06 ,  G06F1/08 ,  G06F1/04

    Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

    Clock generation for timing communications with ranks of memory devices
    149.
    发明授权
    Clock generation for timing communications with ranks of memory devices 有权

    公开(公告)号：US10705990B2

    公开(公告)日：2020-07-07

    申请号：US16228695

    申请日：2018-12-20

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

    IPC: G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F13/16 ,  G11C7/22 ,  G11C7/04 ,  H04L7/033

    Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

    Frequency-agile clock multiplier
    150.
    发明授权
    Frequency-agile clock multiplier 有权

    公开(公告)号：US10608652B2

    公开(公告)日：2020-03-31

    申请号：US16247894

    申请日：2019-01-15

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Masum Hossain

    IPC: H03L7/06 ,  H03L7/099 ,  H03K5/00 ,  H03K5/13 ,  H03K3/03 ,  H03K5/14 ,  H03L7/24 ,  H03L7/16

    Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

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