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公开(公告)号：US11875842B2
公开(公告)日：2024-01-16
申请号：US17522414
申请日：2021-11-09
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Deepanshu Dutta , Tai-Yuan Tseng
IPC: G11C7/12 , G11C11/4096 , G11C11/408 , G11C11/4074 , G11C11/4076
CPC classification number: G11C11/4096 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4087
Abstract: A memory device with one or more planes having sub-blocks is disclosed. The memory device may further include a voltage switch transistor for each of sub-blocks. Additionally, the memory device may further include a row decoder for each of sub-blocks. As a result, an operation to two sub-blocks can be performed at different times. For example, using a row decoder and voltage switch transistor, a sub-block can be initially read, followed by a subsequent read of another sub-block using a separate row decoder and voltage switch transistor. By staggering the read operations through a time delay, the peak current Icc associated with the supply voltage can be reduced.
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公开(公告)号：US20230386568A1
公开(公告)日：2023-11-30
申请号：US17825048
申请日：2022-05-26
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Deepanshu Dutta , Muhammad Masuduzzaman , Jiacen Guo
CPC classification number: G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/08 , G11C16/26
Abstract: A method for programming a memory array of a non-volatile memory structure, wherein the memory array comprises a population of MLC NAND-type memory cells, and the method comprises: (1) in a first program pulse, programming selected memory cells according to a first programmable state and a second programmable state, and (2) in a second program pulse, programming the selected memory cells according to a third programmable state.
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143.发明公开公开(公告)号：US20230326530A1
公开(公告)日：2023-10-12
申请号：US17715647
申请日：2022-04-07
Applicant: SanDisk Technologies LLC
Inventor： Chin-Yi Chen , Muhammad Masuduzzaman , Kou Tei , Deepanshu Dutta , Hiroyuki Mizukoshi , Jiahui Yuan , Xiang Yang
CPC classification number: G11C16/26 , G11C16/08 , G11C16/3459 , G11C16/0483 , G11C16/10 , G11C11/5621
Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in memory holes and grouped into a plurality of tiers. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states to store one bit as single-level cells and a plurality of bits as multi-level cells. The apparatus also includes a control means coupled to the word lines and the memory holes and configured to select a predetermined strobe quantity of the plurality of tiers of the memory cells separately for the memory cells operating as the single-level cells and the memory cells operating as the multi-level cells. The control means is also configured to trigger sensing of the predetermined strobe quantity of the plurality of tiers of the memory cells during a verify operation.
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公开(公告)号：US11551761B1
公开(公告)日：2023-01-10
申请号：US17461418
申请日：2021-08-30
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Xiang Yang , Deepanshu Dutta
IPC: G11C11/04 , G11C16/10 , G11C16/04 , G11C16/26 , G11C16/08 , G11C11/56 , H01L25/065 , H01L27/11582 , H01L27/11565
Abstract: In a non-volatile memory, a block of NAND strings is divided into sub-blocks by etching the select gate layers between sub-blocks. This results in a subset of NAND strings (e.g., at the border of the sub-blocks) having select gates that are partially etched such that the partially etched select gates are partially shaped as compared to the select gates of NAND strings that have not been etched. Host data is programmed to non-volatile memory cells that are connected to an edge word line and are on NAND strings having a complete shaped select gate. Host data is also programmed to non-volatile memory cells that are connected to non-edge word lines. However, host data is not programmed to non-volatile memory cells that are connected to the edge word line and are on NAND strings having a partial shaped select gate.
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公开(公告)号：US20220415398A1
公开(公告)日：2022-12-29
申请号：US17360677
申请日：2021-06-28
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Jiahui Yuan , Deepanshu Dutta
Abstract: A memory device is provided in which blocks of memory cells are divided into separate portions or sub-blocks with respective sets of word line switching transistors. The sub-blocks can be arranged on a substrate on opposite sides of a dividing line, where a separate set of bit lines is provided on each side of the dividing line. Each block has a row decoder which provides a common word line voltage signal to each sub-block of the block. However, each sub-block can have an independent set of word line switching transistors so that the common word line voltage signal can be passed or blocked independently for each sub-block. The blocks of memory cells can be provided on a first die which is inverted and bonded to a second die which includes the sets of word line switching transistors.
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Patent Agency Ranking
146.发明授权公开(公告)号：US11456333B2
公开(公告)日：2022-09-27
申请号：US16903654
申请日：2020-06-17
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Yu-Chung Lien , Jiahui Yuan , Deepanshu Dutta , Christopher Petti
Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive word line layers located over a substrate, and a plurality of vertical memory strings. Each vertical memory string includes a series connection of a memory stack structure and a selector element. Each of the memory stack structures extends through the alternating stack and includes a respective memory film and a respective vertical semiconductor channel. Each of the selector elements includes a two terminal device that is configured to provide at least two different resistivity states.
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公开(公告)号：US11385810B2
公开(公告)日：2022-07-12
申请号：US16916620
申请日：2020-06-30
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Deepanshu Dutta , Huai-Yuan Tseng
IPC: G06F3/06
Abstract: An apparatus includes a controller and a plurality of memory dies operable connected to and controlled by the controller. Each of the memory dies draws a current from a current source during a program operation. The controller being configured to receive a clock signal from each of the memory dies; count the number of clock signal received to determine a count value; and dynamically stagger at least one of the memory dies relative to the other memory dies when the count value reaches a maximum count value within a threshold time. The controller operates to dynamically stagger operation of at least one memory die to prevent the group of memory dies from operating synchronously.
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公开(公告)号：US11361834B1
公开(公告)日：2022-06-14
申请号：US17137871
申请日：2020-12-30
Applicant: SanDisk Technologies LLC
Inventor： Ravi Kumar , Deepanshu Dutta
Abstract: A memory device comprising control circuitry configured to apply a first program voltage to a selected word line, wherein a first subset of memory cells of the selected word line, that correspond to a first set of data states, are inhibited from being programmed with the first program voltage, and wherein the first program voltage is applied to a second subset of memory cells corresponding to a second set of data states. The control circuitry is further configured to cause a first voltage of the selected word line to discharge to a second voltage level corresponding to a second program voltage such that the second program voltage is applied to at least the first subset of memory cells. The control circuitry is further configured to perform a verify operation to verify whether the first subset of memory cells and the second subset of memory cells have completed programming.
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公开(公告)号：US11342035B1
公开(公告)日：2022-05-24
申请号：US17102657
申请日：2020-11-24
Applicant: SanDisk Technologies LLC
Inventor： Xue Bai Pitner , Deepanshu Dutta , Ravi Kumar
Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells each connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control circuit couples to the word lines and the strings determines a program lower tail voltage of a distribution of the threshold voltage following a first program pulse. The control circuit calculates a second program voltage of a second program pulse based on the program lower tail voltage and applies the second program pulse to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells such that the distribution of the threshold voltage of the memory cells have a desired program lower tail voltage without further program pulses.
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公开(公告)号：US20210391012A1
公开(公告)日：2021-12-16
申请号：US16899860
申请日：2020-06-12
Applicant: SanDisk Technologies LLC
Inventor： Muhammad Masuduzzaman , Deepanshu Dutta
Abstract: A storage device may be configured to determine data states for a first set of memory cells, of an array of memory cells, that are part of a logical N−1 neighboring word line that is adjacent to a selected word line. The storage device may be further configured to determine a program voltage configuration based on the data states. The storage device may be further configured to determine, using the program voltage configuration, a program operation on the selected word line to iteratively program respective memory cells, of a second set of memory cells that are part of the selected word line. Determining the data states, determining the program voltage configuration, and performing the program operation may be repeated until a program stop condition is satisfied.
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