公开(公告)号：US20140299938A1

公开(公告)日：2014-10-09

申请号：US13856325

申请日：2013-04-03

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Chengyu Niu ,  Heng Yang

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28132 ,  H01L21/2855 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/41783 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7845 ,  H01L2924/04941 ,  H01L2924/0465 ,  H01L2924/04541 ,  H01L2924/01074 ,  H01L2924/04953 ,  H01L2924/01029 ,  H01L2924/01022 ,  H01L2924/01007 ,  H01L2924/0505 ,  H01L2924/01013

Abstract: Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device may include a metallic gate and a channel strained in a first manner. The second type of device may include a metallic gate and a channel strained in a second manner. The gates may include, collectively, three or fewer metallic materials. The gates may share a same metallic material. A method of forming the semiconductor devices on an integrated circuit may include depositing first and second metallic layers in first and second regions of the integrated circuit corresponding to the first and second gates, respectively.

Abstract translation: 增强载流子迁移率的方法和装置。 集成电路可以包括两种类型的半导体器件。 第一类型的装置可以包括金属门和以第一方式应变的通道。 第二类型的装置可以包括金属门和以第二方式应变的通道。 这些门可以共同地包括三种或更少的金属材料。 门可以共享相同的金属材料。 在集成电路上形成半导体器件的方法可以包括分别在对应于第一和第二栅极的集成电路的第一和第二区域中沉积第一和第二金属层。

公开(公告)号：US20140134808A1

公开(公告)日：2014-05-15

申请号：US14157947

申请日：2014-01-17

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Yiheng Xu ,  Carl Radens ,  Lawrence A. Clevenger

IPC: H01L29/66 ,  H01L21/28

CPC classification number: H01L29/66666 ,  H01L21/28008 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/7781

Abstract: A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.

Abstract translation: 一种半导体器件，其具有位于源极区域和漏极区域之间的与栅极电极的两侧相邻的凹部中的栅极。 沟道区域低于源极区域的大部分以及漏极区域和整个栅极电极的大部分。

公开(公告)号：US20140084465A1

公开(公告)日：2014-03-27

申请号：US13629402

申请日：2012-09-27

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76816 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295

Abstract: A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between metal tracks in the metal layers above and below the intermediate metal layer.

Abstract translation: 多个金属轨道形成在集成电路管芯内，堆叠在管芯内的三个金属层。 在中间金属层的金属轨道周围形成保护电介质层。 保护性介电层用作硬掩模，以在中间金属层之上和之下的金属层中限定金属轨道之间的接触通孔。

公开(公告)号：US20140084247A1

公开(公告)日：2014-03-27

申请号：US13931234

申请日：2013-06-28

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L29/775 ,  H01L21/66

CPC classification number: H01L29/66492 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823842 ,  H01L22/12 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/413 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66431 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7781 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase Vt. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease Vt. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies Vt. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.

Abstract translation: 将金属量子点（例如，溴化银（AgBr）膜）引入MOSFET的源极和漏极区域可以通过调整阈值电压来帮助控制晶体管的性能。 如果溴化银膜富含溴原子，则沉积阴离子量子点，改变AgBr能隙以增加Vt，如果溴化银膜富含银原子，则沉积阳离子量子点，AgBr 能量间隙被改变以便降低Vt，不同尺寸的中性量子点的原子层沉积（ALD）也变化Vt。在膜沉积期间使用质谱仪可以帮助改变量子点膜的组成。 金属量子点可以结合到离子掺杂的源极和漏极区域中。 或者，金属量子点可以并入外延掺杂的源区和漏区。

公开(公告)号：US20140084245A1

公开(公告)日：2014-03-27

申请号：US13931096

申请日：2013-06-28

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L29/775 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/127 ,  H01L29/165 ,  H01L29/401 ,  H01L29/413 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66431 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/78696

Abstract: Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.

Abstract translation: 金属量子点被并入到MOSFET阵列的掺杂源极和漏极区域中，以通过改变半导体晶体的能隙来帮助控制晶体管的性能。 在第一示例中，量子点被并入到离子掺杂的源极和漏极区域中。 在第二个例子中，量子点被并入外延掺杂的源区和漏区。

公开(公告)号：US11695053B2

公开(公告)日：2023-07-04

申请号：US17948961

申请日：2022-09-20

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/45 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/768 ,  C23C14/04 ,  C23C14/22 ,  H01L29/66

CPC classification number: H01L29/51 ,  C23C14/048 ,  C23C14/221 ,  H01L21/02521 ,  H01L21/02631 ,  H01L21/285 ,  H01L21/2855 ,  H01L21/28088 ,  H01L21/76831 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance. A work function semiconductor material such as a silver bromide or a lanthanum oxide is deposited so as to include clusters of different sizes such as dimers, trimers, and tetramers, formed from isolated monomers. A type of Atomic Layer Deposition system is used to deposit on semiconductor wafers molecular clusters to form thin film junctions having selected energy gaps. A beam of ions contains different ionic clusters which are then selected for deposition by passing the beam through a filter in which different apertures select clusters based on size and orientation.

公开(公告)号：US10741698B2

公开(公告)日：2020-08-11

申请号：US16355398

申请日：2019-03-15

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L29/66 ,  H01L29/788 ,  H01L27/088

Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.

公开(公告)号：US10700214B2

公开(公告)日：2020-06-30

申请号：US15945937

申请日：2018-04-05

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/24 ,  H01L29/49 ,  H01L27/146 ,  H01L29/423 ,  H01L27/12 ,  H01L21/8234

Abstract: Processes and overturned thin film device structures generally include a gate having a concave shape defined by three faces. The processes generally include forming the overturned thin film device structures such that the channel self-aligns to the gate and the source/drain contacts include a self-aligned step height.

公开(公告)号：US10553497B2

公开(公告)日：2020-02-04

申请号：US15276516

申请日：2016-09-26

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang ,  Chengyu Niu ,  Heng Yang

IPC: H01L21/70 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L29/78 ,  H01L21/285 ,  H01L29/417 ,  H01L29/66 ,  H01L27/092

Abstract: Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device may include a metallic gate and a channel strained in a first manner. The second type of device may include a metallic gate and a channel strained in a second manner. The gates may include, collectively, three or fewer metallic materials. The gates may share a same metallic material. A method of forming the semiconductor devices on an integrated circuit may include depositing first and second metallic layers in first and second regions of the integrated circuit corresponding to the first and second gates, respectively.

公开(公告)号：US10411140B2

公开(公告)日：2019-09-10

申请号：US15892028

申请日：2018-02-08

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  John H. Zhang

IPC: B81B7/02 ,  H01L29/84 ,  H01H59/00 ,  B82B3/00 ,  H01H1/00 ,  H01H49/00 ,  H01L21/02 ,  H01L21/306 ,  H01H50/00

Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.