Multichannel memory arbitration and interleaving scheme

    公开(公告)号:US11960416B2

    公开(公告)日:2024-04-16

    申请号:US17558278

    申请日:2021-12-21

    CPC classification number: G06F13/1647

    Abstract: Techniques including a memory controller with a set of memory channel queues, wherein memory channel queues of the set of memory channel queues correspond to memory channels to access a set of memory modules, a first arbitration module, and a second arbitration module. The memory controller is configured to receive a first memory request from the peripheral and place one or more portions of the first memory request in the memory channel queues of the set of memory channel queues. The first arbitration module is configured to determine an arbitration algorithm, select a first memory channel queue based on the arbitration algorithm, present the one or more portions of the first memory request in the selected first memory channel queue to the second arbitration module, and output the presented one or more portions of the first memory request based on a selection by the second arbitration module.

    In-line chromatic aberration correction in wide dynamic range (WDR) image processing pipeline

    公开(公告)号:US11743612B2

    公开(公告)日:2023-08-29

    申请号:US17555145

    申请日:2021-12-17

    CPC classification number: H04N25/611 G06T1/60 G06T3/4015 H04N25/13

    Abstract: In the advanced driver-assistance systems (ADAS) field, RAW sensor image processing for machine vision (MV) applications can be of critical importance. Due to red/green/blue (RGB) image components being focused by the lens at different locations in image plane, the lateral chromatic aberration (LCA) phenomenon may sometimes be observed, which causes false color around edges in the final image output, especially for high contrast edges, which can impede MV applications. Disclosed herein are low-latency, efficient, optimized designs for chromatic aberration correction (CAC) modules. In some embodiments, an in-pipeline CAC design is used that: is configured to perform on-the-fly CAC without any out-of-pipeline memory traffic; enables use of wide dynamic range (WDR) sensors; uses bicubic interpolation; supports vertical and horizontal chromatic aberration red/blue color channel offsets, reduces CAC line memory requirements, and supports flexible look-up table (LUT) down-sampling factors to improve the spatial precision of correction and accommodate popular image sensor resolutions.

    METHOD AND APPARATUS OF HEVC DE-BLOCKING FILTER

    公开(公告)号:US20230232022A1

    公开(公告)日:2023-07-20

    申请号:US18123432

    申请日:2023-03-20

    Abstract: A method of de-blocking filtering a processed video is provided. The processed video includes a plurality of blocks and each block includes a plurality of sub-blocks. A current block of the plurality of blocks includes vertical edges and horizontal edges. The processed video further includes a set of control parameters and reconstructed pixels corresponding to the current block. A boundary strength index is estimated at the vertical edges and at the horizontal edges of the current block. The set of control parameters, the reconstructed pixels corresponding to the current block and partially filtered pixels corresponding to a set of adjacent sub-blocks are loaded. The vertical edges and the horizontal edges of the current block are filtered based on the boundary strength index and the set of control parameters such that a vertical edge of the current block is filtered before filtering at least one horizontal edge of the current block.

    Configurable multi-function PCIe endpoint controller in an SoC

    公开(公告)号:US11704263B2

    公开(公告)日:2023-07-18

    申请号:US17697114

    申请日:2022-03-17

    Abstract: A configurable multi-function Peripheral Component Interchange Express (PCIe) endpoint controller, integrated in a system-on-chip (SoC), that exposes multiple functions of multiple processing subsystems (e.g., peripherals) to a host. The SoC may include a centralized transaction tunneling unit and a multi-function interrupt manager. The processing subsystems output data to the host via the centralized transaction tunneling unit, which translates addresses provided by the host to a local address of the SoC. Therefore, the centralized transaction tunneling unit enables those processing subsystems to consume addresses provided by the host without the need for software intervention and software-based translation. The SoC may also provide isolation between each function provided by the processing systems. The multi-function interrupt manager enables the endpoint controller to propagate interrupt messages received from the processing subsystems to the host.

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