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公开(公告)号:US11960416B2
公开(公告)日:2024-04-16
申请号:US17558278
申请日:2021-12-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Daniel Brad Wu , Abhishek Shankar , Mihir Narendra Mody , Gregory Raymond Shurtz , Jason A. T. Jones , Hemant Vijay Kumar Hariyani
IPC: G06F13/16
CPC classification number: G06F13/1647
Abstract: Techniques including a memory controller with a set of memory channel queues, wherein memory channel queues of the set of memory channel queues correspond to memory channels to access a set of memory modules, a first arbitration module, and a second arbitration module. The memory controller is configured to receive a first memory request from the peripheral and place one or more portions of the first memory request in the memory channel queues of the set of memory channel queues. The first arbitration module is configured to determine an arbitration algorithm, select a first memory channel queue based on the arbitration algorithm, present the one or more portions of the first memory request in the selected first memory channel queue to the second arbitration module, and output the presented one or more portions of the first memory request based on a selection by the second arbitration module.
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142.
公开(公告)号:US11743612B2
公开(公告)日:2023-08-29
申请号:US17555145
申请日:2021-12-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Gang Hua , Rajasekhar Reddy Allu , Mihir Narendra Mody , Niraj Nandan , Mayank Mangla , Pandy Kalimuthu
IPC: H04N25/611 , G06T3/40 , G06T1/60 , H04N25/13
CPC classification number: H04N25/611 , G06T1/60 , G06T3/4015 , H04N25/13
Abstract: In the advanced driver-assistance systems (ADAS) field, RAW sensor image processing for machine vision (MV) applications can be of critical importance. Due to red/green/blue (RGB) image components being focused by the lens at different locations in image plane, the lateral chromatic aberration (LCA) phenomenon may sometimes be observed, which causes false color around edges in the final image output, especially for high contrast edges, which can impede MV applications. Disclosed herein are low-latency, efficient, optimized designs for chromatic aberration correction (CAC) modules. In some embodiments, an in-pipeline CAC design is used that: is configured to perform on-the-fly CAC without any out-of-pipeline memory traffic; enables use of wide dynamic range (WDR) sensors; uses bicubic interpolation; supports vertical and horizontal chromatic aberration red/blue color channel offsets, reduces CAC line memory requirements, and supports flexible look-up table (LUT) down-sampling factors to improve the spatial precision of correction and accommodate popular image sensor resolutions.
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143.
公开(公告)号:US11714776B2
公开(公告)日:2023-08-01
申请号:US17564975
申请日:2021-12-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Kishon Vijay Abraham Israel Vijayponraj , Sriramakrishnan Govindarajan , Mihir Narendra Mody
IPC: G06F13/42 , G06F9/4401 , G06F13/40 , G06F12/1027
CPC classification number: G06F13/4247 , G06F12/1027 , G06F13/4022 , G06F2213/0024 , G06F2213/0026 , G06F2213/0038
Abstract: A system-on-chip (SoC) may be configured to enable a Multi-Chip Daisy Chain Topology using peripheral component interface express (PCIe). The SoC may include a processor, a local memory, a root complex operably connected to the processor and the local memory, and a multi-function endpoint controller. The root complex may obtain forwarding information to configure routing of transactions to one or more PCIe endpoint functions or to the local memory. The root complex may initialize, based on the forwarding information, access between a host and the one or more PCIe endpoint functions. The multi-function endpoint controller may obtain a descriptor and endpoint information to configure outbound portals for transactions to at least one remote host. The multi-function endpoint controller may establish a communication path between the host and a function out of a plurality of functions.
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公开(公告)号:US20230232022A1
公开(公告)日:2023-07-20
申请号:US18123432
申请日:2023-03-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Mihir Narendra Mody , Niraj Nandan , Hideo Tamama
IPC: H04N19/176 , H04N19/14 , H04N19/82 , H04N19/86 , H04N19/117
CPC classification number: H04N19/176 , H04N19/14 , H04N19/82 , H04N19/86 , H04N19/117 , H04N19/186
Abstract: A method of de-blocking filtering a processed video is provided. The processed video includes a plurality of blocks and each block includes a plurality of sub-blocks. A current block of the plurality of blocks includes vertical edges and horizontal edges. The processed video further includes a set of control parameters and reconstructed pixels corresponding to the current block. A boundary strength index is estimated at the vertical edges and at the horizontal edges of the current block. The set of control parameters, the reconstructed pixels corresponding to the current block and partially filtered pixels corresponding to a set of adjacent sub-blocks are loaded. The vertical edges and the horizontal edges of the current block are filtered based on the boundary strength index and the set of control parameters such that a vertical edge of the current block is filtered before filtering at least one horizontal edge of the current block.
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公开(公告)号:US11704263B2
公开(公告)日:2023-07-18
申请号:US17697114
申请日:2022-03-17
Applicant: Texas Instruments Incorporated
Inventor: Sriramakrishnan Govindarajan , Kishon Vijay Abraham Israel Vijayponraj , Mihir Narendra Mody
CPC classification number: G06F13/20 , G06F13/4221 , G06F13/4282 , G06F2213/0024 , G06F2213/0026
Abstract: A configurable multi-function Peripheral Component Interchange Express (PCIe) endpoint controller, integrated in a system-on-chip (SoC), that exposes multiple functions of multiple processing subsystems (e.g., peripherals) to a host. The SoC may include a centralized transaction tunneling unit and a multi-function interrupt manager. The processing subsystems output data to the host via the centralized transaction tunneling unit, which translates addresses provided by the host to a local address of the SoC. Therefore, the centralized transaction tunneling unit enables those processing subsystems to consume addresses provided by the host without the need for software intervention and software-based translation. The SoC may also provide isolation between each function provided by the processing systems. The multi-function interrupt manager enables the endpoint controller to propagate interrupt messages received from the processing subsystems to the host.
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公开(公告)号:US11693787B2
公开(公告)日:2023-07-04
申请号:US17171185
申请日:2021-02-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Sriramakrishnan Govindarajan , Gregory Raymond Shurtz , Mihir Narendra Mody , Charles Lance Fuoco , Donald E. Steiss , Jonathan Elliot Bergsagel , Jason A.T. Jones
IPC: G06F12/1027 , G06F9/455
CPC classification number: G06F12/1027 , G06F9/45558 , G06F2009/45583 , G06F2212/657
Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.
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147.
公开(公告)号:US11682212B2
公开(公告)日:2023-06-20
申请号:US17086560
申请日:2020-11-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Hetul Sanghvi , Mihir Narendra Mody , Niraj Nandan , Anish Reghunath , Michael Peter Lachmayr
CPC classification number: G06V20/52 , G06T1/0007 , G06T7/20 , G06T7/269 , G06V20/64 , G06T2200/28 , G06T2207/10004 , G06T2207/20016 , G06T2207/20032 , G06T2207/30252
Abstract: A computer vision system is provided that includes an image generation device configured to capture consecutive two dimensional (2D) images of a scene, a first memory configured to store the consecutive 2D images, a second memory configured to store a growing window of consecutive rows of a reference image and a growing window of consecutive rows of a current image, wherein the reference image and the current image are a pair of consecutive 2D images stored in the first memory, a third memory configured to store a sliding window of pixels fetched from the growing window of the reference image, wherein the pixels in the sliding window are stored in tiles, and a dense optical flow engine (DOFE) configured to determine a dense optical flow map for the pair of consecutive 2D images, wherein the DOFE uses the sliding window as a search window for pixel correspondence searches.
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公开(公告)号:US11669370B2
公开(公告)日:2023-06-06
申请号:US17012223
申请日:2020-09-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Niraj Nandan , Hetul Sanghvi , Mihir Narendra Mody
CPC classification number: G06F9/5044 , G06F9/4887 , G06F9/52 , G06F11/0757
Abstract: A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image data remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.
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公开(公告)号:US11656925B2
公开(公告)日:2023-05-23
申请号:US17138036
申请日:2020-12-30
Applicant: Texas Instruments Incorporated
Inventor: Kedar Satish Chitnis , Charles Lance Fuoco , Sriramakrishnan Govindarajan , Mihir Narendra Mody , William A. Mills , Gregory Raymond Shurtz , Amritpal Singh Mundra
CPC classification number: G06F9/546 , G06F9/3836 , G06F9/45558 , G06F9/4806 , G06F9/5027 , G06F2009/45583 , G06F2009/45587
Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.
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公开(公告)号:US11653105B2
公开(公告)日:2023-05-16
申请号:US17110139
申请日:2020-12-02
Applicant: Texas Instruments Incorporated
Inventor: Gang Hua , Shashank Dabral , Mihir Narendra Mody , Rajasekhar Reddy Allu , Niraj Nandan
CPC classification number: H04N23/88 , H04N9/78 , H04N23/71 , H04N23/741 , H04N23/76
Abstract: A method for local automatic white balance (AWB) of wide dynamic range (WDR) images is provided that includes collecting statistics for local AWB by an image signal processor (ISP) from a first WDR image generated by the ISP, receiving, by the ISP, a plurality of local gain lookup tables (LUTs), one for each color channel, wherein the plurality of local gain LUTs is generated using the statistics, and applying, by the ISP, a gain value to each pixel in a second WDR image generated by the ISP, wherein the gain value for the pixel is determined by the ISP using the local gain LUT for the color channel of the pixel.
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