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    Semiconductor memory device and method for manufacturing the same
    141.
    发明授权
    Semiconductor memory device and method for manufacturing the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US08901635B2

    公开(公告)日：2014-12-02

    申请号：US13414988

    申请日：2012-03-08

    申请人： Jun Fujiki ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Tomoko Fujiwara

    发明人： Jun Fujiki ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Tomoko Fujiwara

    IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/66

    CPC分类号： H01L29/7926 ,  H01L27/11582 ,  H01L29/66833

    摘要： According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, an insulating film, and a charge storage film. The stacked body includes a plurality of electrode films stacked with an inter-layer insulating film provided between the electrode films. The semiconductor pillar pierces the stacked body. The insulating film is provided between the semiconductor pillar and the electrode films on an outer side of the semiconductor pillar with a gap interposed. The charge storage film is provided between the insulating film and the electrode films. The semiconductor pillar includes germanium. An upper end portion of the semiconductor pillar is supported by an interconnect provided above the stacked body.

    摘要翻译： 根据一个实施例，半导体存储器件包括堆叠体，半导体柱，绝缘膜和电荷存储膜。 层叠体包括层叠了设置在电极膜之间的层间绝缘膜的多个电极膜。 半导体柱穿透层叠体。 绝缘膜设置在半导体柱和位于半导体柱的外侧的电极膜之间，间隙插入。 电荷存储膜设置在绝缘膜和电极膜之间。 半导体柱包括锗。 半导体柱的上端部由设置在层叠体上方的配线支撑。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
    142.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20130062681A1

    公开(公告)日：2013-03-14

    申请号：US13414988

    申请日：2012-03-08

    申请人： Jun Fujiki ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Tomoko Fujiwara

    发明人： Jun Fujiki ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Tomoko Fujiwara

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L29/7926 ,  H01L27/11582 ,  H01L29/66833

    摘要： According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, an insulating film, and a charge storage film. The stacked body includes a plurality of electrode films stacked with an inter-layer insulating film provided between the electrode films. The semiconductor pillar pierces the stacked body. The insulating film is provided between the semiconductor pillar and the electrode films on an outer side of the semiconductor pillar with a gap interposed. The charge storage film is provided between the insulating film and the electrode films. The semiconductor pillar includes germanium. An upper end portion of the semiconductor pillar is supported by an interconnect provided above the stacked body.

    摘要翻译： 根据一个实施例，半导体存储器件包括堆叠体，半导体柱，绝缘膜和电荷存储膜。 层叠体包括层叠了设置在电极膜之间的层间绝缘膜的多个电极膜。 半导体柱穿透层叠体。 绝缘膜设置在半导体柱和位于半导体柱的外侧的电极膜之间，间隙插入。 电荷存储膜设置在绝缘膜和电极膜之间。 半导体柱包括锗。 半导体柱的上端部由设置在层叠体上方的配线支撑。

    Semiconductor memory device
    143.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08767452B2

    公开(公告)日：2014-07-01

    申请号：US13418651

    申请日：2012-03-13

    申请人： Masaru Kito ,  Tomoko Fujiwara ,  Hideaki Aochi

    发明人： Masaru Kito ,  Tomoko Fujiwara ,  Hideaki Aochi

    IPC分类号： G11C11/14 ,  G11C11/00

    CPC分类号： H01L27/11565 ,  G11C5/025 ,  H01L27/11582 ,  H01L29/7926

    摘要： According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a charge storage layer, a tunneling layer, a dividing trench and a first heating unit. The stacked body includes a plurality of first insulating films stacked alternately with a plurality of electrode films. The semiconductor pillar pierces the stacked body. The charge storage layer is provided between the electrode films and the semiconductor pillar. The tunneling layer is provided between the charge storage layer and the semiconductor pillar. The dividing trench is provided between the semiconductor pillars in one direction orthogonal to a stacking direction of the stacked body to divide the electrode films. The first heating unit is provided in an interior of the dividing trench.

    摘要翻译： 根据一个实施例，半导体存储器件包括堆叠体，半导体柱，电荷存储层，隧道层，分隔沟槽和第一加热单元。 层叠体包括与多个电极膜交替堆叠的多个第一绝缘膜。 半导体柱穿透层叠体。 电荷存储层设置在电极膜和半导体柱之间。 隧道层设置在电荷存储层和半导体柱之间。 在与层叠体的堆叠方向正交的一个方向上的半导体柱之间设置分割沟槽，以分割电极膜。 第一加热单元设置在分隔沟槽的内部。

    Nonvolatile semiconductor memory device and method of data write therein
    144.
    发明授权
    Nonvolatile semiconductor memory device and method of data write therein 有权
    非易失性半导体存储器件及其中的数据写入方法

    公开(公告)号：US08760924B2

    公开(公告)日：2014-06-24

    申请号：US13427263

    申请日：2012-03-22

    申请人： Hitoshi Iwai ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Masaru Kito

    发明人： Hitoshi Iwai ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Masaru Kito

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3454 ,  G11C16/0483 ,  G11C16/06

    摘要： A memory cell comprises a first semiconductor layer, and a first conductive layer. The first semiconductor layer extends in a perpendicular direction with respect to a semiconductor substrate. The first conductive layer sandwiches a charge storage layer with the first semiconductor layer. A control circuit executes a first program operation and then executes a second program operation. The first program operation supplies a first voltage to the body of the memory cell and supplies a second voltage larger than the first voltage to the gate of the memory cell. The second program operation renders the body of the memory cell in a floating state and supplies a third voltage which is positive to the gate of the memory cell.

    摘要翻译： 存储单元包括第一半导体层和第一导电层。 第一半导体层相对于半导体衬底在垂直方向上延伸。 第一导电层与第一半导体层夹着电荷存储层。 控制电路执行第一程序操作，然后执行第二程序操作。 第一编程操作向存储单元的主体提供第一电压，并将大于第一电压的第二电压提供给存储单元的栅极。 第二程序操作使存储器单元的主体呈浮置状态，并向存储器单元的栅极提供为正的第三电压。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DATA WRITE THEREIN
    145.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DATA WRITE THEREIN 有权
    非易失性半导体存储器件及其数据写入方法

    公开(公告)号：US20130021848A1

    公开(公告)日：2013-01-24

    申请号：US13427263

    申请日：2012-03-22

    申请人： Hitoshi IWAI ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Masaru Kito

    发明人： Hitoshi IWAI ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Masaru Kito

    IPC分类号： G11C16/06 ,  G11C16/04

    CPC分类号： G11C16/3454 ,  G11C16/0483 ,  G11C16/06

    摘要： A memory cell comprises a first semiconductor layer, and a first conductive layer. The first semiconductor layer extends in a perpendicular direction with respect to a semiconductor substrate. The first conductive layer sandwiches a charge storage layer with the first semiconductor layer. A control circuit executes a first program operation and then executes a second program operation. The first program operation supplies a first voltage to the body of the memory cell and supplies a second voltage larger than the first voltage to the gate of the memory cell. The second program operation renders the body of the memory cell in a floating state and supplies a third voltage which is positive to the gate of the memory cell.

    摘要翻译： 存储单元包括第一半导体层和第一导电层。 第一半导体层相对于半导体衬底在垂直方向上延伸。 第一导电层与第一半导体层夹着电荷存储层。 控制电路执行第一程序操作，然后执行第二程序操作。 第一编程操作向存储单元的主体提供第一电压，并将大于第一电压的第二电压提供给存储单元的栅极。 第二程序操作使存储器单元的主体呈浮置状态，并向存储器单元的栅极提供为正的第三电压。

    Semiconductor memory device
    146.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08581305B2

    公开(公告)日：2013-11-12

    申请号：US13046894

    申请日：2011-03-14

    申请人： Yoshiaki Fukuzumi ,  Hideaki Aochi

    发明人： Yoshiaki Fukuzumi ,  Hideaki Aochi

    IPC分类号： H01L23/525

    CPC分类号： H01L27/2463 ,  G11C13/0007 ,  G11C16/04 ,  G11C2213/73 ,  H01L23/525 ,  H01L23/528 ,  H01L27/2436 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor memory device according to one embodiment of the present invention includes a dielectric film configured to store information depending on presence or absence of a conductive path therein, and a plurality of electrodes provided to contact a first surface of the dielectric film. The conductive path can be formed between two electrodes arbitrarily selected form the plurality of electrodes. The conductive path has a rectifying property of allowing a current to flow more easily in a first direction connecting arbitrary two electrodes than in a second direction opposite to the first direction. The largest possible number of the conductive paths that may be formed is larger than the number of the plurality of electrodes.

    摘要翻译： 根据本发明的一个实施例的半导体存储器件包括：电介质膜，被配置为根据存在或不存在导电路径来存储信息;以及多个电极，设置成与电介质膜的第一表面接触。 导电路径可以形成在从多个电极任意选择的两个电极之间。 导电路径具有使电流在连接任意两个电极的第一方向上比在与第一方向相反的第二方向更容易流动的整流特性。 可能形成的最大可能数量的导电路径大于多个电极的数量。

    NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
    147.
    发明申请
    NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    非挥发性半导体存储器件及其制造方法

    公开(公告)号：US20120008400A1

    公开(公告)日：2012-01-12

    申请号：US12886854

    申请日：2010-09-21

    申请人： Yoshiaki FUKUZUMI ,  Ryota Katsumata ,  Megumi Ishiduki ,  Hideaki Aochi

    发明人： Yoshiaki FUKUZUMI ,  Ryota Katsumata ,  Megumi Ishiduki ,  Hideaki Aochi

    IPC分类号： G11C16/04 ,  H01L29/792 ,  H01L21/336

    CPC分类号： H01L27/11578 ,  G11C16/0483 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

    摘要： A non-volatile semiconductor storage device includes: a memory string; a select transistor; and a carrier selection element. The select transistor has one end connected to one end of the memory string. The carrier selection element has one end connected to the other end of the select transistor, and selects a majority carrier flowing through respective bodies of the memory transistors and the select transistor. The carrier selection element includes: a third semiconductor layer; a metal layer; a second gate insulation layer; and a third conductive layer. The metal layer extends in the vertical direction. The metal layer extends in the vertical direction from the top of the third semiconductor layer. The second gate insulation layer surrounds the third semiconductor layer and the metal layer. The third conductive layer surrounds the third semiconductor layer and the metal layer via the second gate insulation layer and extends in a parallel direction.

    摘要翻译： 非易失性半导体存储装置包括：存储器串; 选择晶体管; 和载波选择元件。 选择晶体管的一端连接到存储器串的一端。 载波选择元件的一端连接到选择晶体管的另一端，并且选择流过存储晶体管和选择晶体管的相应体的多数载流子。 载体选择元件包括：第三半导体层; 金属层; 第二栅绝缘层; 和第三导电层。 金属层沿垂直方向延伸。 金属层从第三半导体层的顶部沿垂直方向延伸。 第二栅极绝缘层包围第三半导体层和金属层。 第三导电层经由第二栅极绝缘层围绕第三半导体层和金属层，并沿平行方向延伸。