公开(公告)号：US5944798A

公开(公告)日：1999-08-31

申请号：US802673

申请日：1997-02-19

Applicant: James F. McCarty ,  William C. Galloway

Inventor： James F. McCarty ,  William C. Galloway

IPC: H04L12/433 ,  G06F11/00

CPC classification number: H04L12/433

Abstract: A computer system with a plurality of devices compatible with the Fibre Channel Protocol. The computer system is provided with the capability to recover from a loop hang condition resulting from an unresponsive communication link in an Arbitrated Loop. This capability is realized by providing a sense mechanism for detecting a no-change condition in the states associated with a controller arranged in the Arbitrated Loop.

Abstract translation: 具有与光纤通道协议兼容的多个设备的计算机系统。 计算机系统具有从仲裁环路中无响应的通信链路导致的循环挂起状况恢复的能力。 该能力通过提供用于检测与布置在仲裁环路中的控制器相关联的状态中的无变化状态的感测机制来实现。

公开(公告)号：US5930115A

公开(公告)日：1999-07-27

申请号：US54735

申请日：1998-04-03

Applicant: Mark S. Tracy ,  Minh H Nguyen ,  Curtis L. Progl

Inventor： Mark S. Tracy ,  Minh H Nguyen ,  Curtis L. Progl

IPC: G06F1/20 ,  H01L23/34 ,  H01L23/40 ,  H05K7/20

CPC classification number: H05K7/20727 ,  G06F1/203 ,  G06F1/206 ,  H01L23/34 ,  H01L23/4006 ,  H01L2023/4043 ,  H01L2023/4062 ,  H01L2023/4068 ,  H01L2023/4087 ,  H01L2924/0002

Abstract: A thermal management structure to provide mechanical isolation and heat removal for an unpackaged semiconductor die mounted directly on a printed circuit board substrate. The thermal management structure sandwiches the unpackaged semiconductor die and substrate between two heat sink pieces which are rigidly mounted to the substrate, thereby mechanically isolating the unpackaged semiconductor die and preventing the die from being accidentally touched. The two heat sink pieces further compliantly thermally engage selected sites on the exposed face of the semiconductor die and the surface of the substrate to conductively remove heat away from the substrate. The thermal management structure may also provide electromagnetic shielding which isolates the electromagnetic fields generated by the substrate from electromagnetic fields external to the thermal management structure. The thermal management structure may also thermally engage selected thermally conductive components within an end product to spread the heat more uniformly throughout the system.

Abstract translation: 用于为直接安装在印刷电路板基板上的未封装的半导体管芯提供机械隔离和散热的热管理结构。 热管理结构将未封装的半导体管芯和衬底夹在刚性地安装到衬底的两个散热片之间，从而机械地隔离未封装的半导体管芯并防止管芯被意外触摸。 两个散热片进一步顺从地热接合半导体管芯的暴露表面上的选定部位和衬底的表面，从而导电地移除远离衬底的热量。 热管理结构还可以提供电磁屏蔽，其将由衬底产生的电磁场与热管理结构外部的电磁场隔离。 热管理结构还可以使端部产品内的选定的导热部件热接合，从而在整个系统中更均匀地散热。

公开(公告)号：US5905509A

公开(公告)日：1999-05-18

申请号：US941860

申请日：1997-09-30

Applicant: Phillip M. Jones ,  Robert Allan Lester ,  Kenneth Tom Chin

Inventor： Phillip M. Jones ,  Robert Allan Lester ,  Kenneth Tom Chin

IPC: G06F12/10 ,  G06F13/14 ,  G06F12/08

CPC classification number: G06F12/1027 ,  G06F12/1081 ,  G06F2212/681

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page. The core logic chipset caches a subset of the most recently used GART table entries to increase AGP performance when performing the address translation. The core logic chipset uses a two-level GART cache comprising a plurality of first-level GART caches and a common second level GART cache. Each of the plurality of first-level GART caches are coupled to a respective interface in the computer system and effectively de-couple the different interface GART address translations so that GART cache thrashing and cache arbitration delays are substantially reduced. Separate decoupled first-level GART caches for each interface allow concurrent GART address translations among the different interfaces. Individual first-level GART caches may be fined tuned for each associated interface.

Abstract translation: 具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向存储器中的图形数据页面的基地址的地址指针，以及可用于定制关联页面的特征标记。 核心逻辑芯片组缓存最近使用的GART表项的子集，以在执行地址转换时增加AGP性能。 核心逻辑芯片组使用包括多个第一级GART高速缓存和公共第二级GART高速缓存的双级GART缓存。 多个第一级GART高速缓存中的每一个耦合到计算机系统中的相应接口，并且有效地解耦不同的接口GART地址转换，使得GART高速缓存颠簸和高速缓存仲裁延迟显着降低。 对于每个接口，单独的解耦第一级GART缓存允许在不同接口之间进行并发GART地址转换。 单个第一级GART缓存可能会针对每个相关联的接口进行调整。

公开(公告)号：US5900885A

公开(公告)日：1999-05-04

申请号：US708122

申请日：1996-09-03

Applicant: James L. Stortz

Inventor： James L. Stortz

IPC: G06F12/00 ,  G09G5/36 ,  G09G5/39 ,  H04N5/907 ,  G06F13/00

CPC classification number: G09G5/36 ,  G09G2360/123 ,  G09G2360/125

Abstract: A method for providing a video buffer includes reserving an incremental video buffer in system memory, and controlling the use of a dedicated video buffer and the incremental video buffer to provide a composite video buffer.

Abstract translation: 一种用于提供视频缓冲器的方法包括在系统存储器中预留增量视频缓冲器，并且控制专用视频缓冲器和增量视频缓冲器的使用以提供复合视频缓冲器。

公开(公告)号：US5872941A

公开(公告)日：1999-02-16

申请号：US659141

申请日：1996-06-05

Applicant: Alan L. Goodrum ,  John M. MacLaren ,  Christopher J. Pettey ,  Paul R. Culley

Inventor： Alan L. Goodrum ,  John M. MacLaren ,  Christopher J. Pettey ,  Paul R. Culley

IPC: G06F13/36 ,  G06F13/362 ,  G06F13/364 ,  G06F13/40 ,  G06F13/00 ,  G06F13/16

CPC classification number: G06F13/364 ,  G06F13/4054

Abstract: A computer system includes a data storage device on a first data bus, a requesting device that initiates a delayed request on a second data bus, and a bridge device that delivers the delayed request to the first data bus and, after the requesting device regains control of the second data bus, begins providing data to the requesting device while the data storage device is providing the requested data to the bridge device.

Abstract translation: 计算机系统包括在第一数据总线上的数据存储设备，在第二数据总线上启动延迟请求的请求设备，以及将延迟的请求传送到第一数据总线的桥接设备，并且在请求设备重新获得控制之后 的第二数据总线开始向数据存储设备提供所请求的数据到桥接设备时向请求设备提供数据。

公开(公告)号：US5867728A

公开(公告)日：1999-02-02

申请号：US768308

申请日：1996-12-17

Applicant: Maria L. Melo ,  James R. Reif

Inventor： Maria L. Melo ,  James R. Reif

IPC: G06F13/40 ,  G06F13/00

CPC classification number: G06F13/4027

Abstract: To assure that memory and/or I/O cycles will run correctly after a PCI device configuration cycle that changes memory and/or I/O mapping, in a multi-processor P6 computer system that pipelines instructions. The memory and I/O cycles are suspended on the processor bus until the configuration cycle has been completed. A signal is generated within the address decode logic to prevent address decoding from taking place if a PCI device is being configured. During the configuration transactions, other pipelined transaction cycles are snoop stalled until the PCI configuration write has been completed.

Abstract translation: 为了确保内存和/或I / O周期在更改内存和/或I / O映射的PCI设备配置周期后能够在管理指令的多处理器P6计算机系统中正常运行。 存储器和I / O周期暂停在处理器总线上，直到配置周期完成。 在地址解码逻辑中产生信号，以防止在配置PCI设备时发生地址解码。 在配置事务期间，其他流水线事务周期被窥探停止，直到PCI配置写入完成。

公开(公告)号：US5867675A

公开(公告)日：1999-02-02

申请号：US692488

申请日：1996-08-06

Applicant: Lawrence W. Lomelino ,  Ryan A. Callison

Inventor： Lawrence W. Lomelino ,  Ryan A. Callison

IPC: G06F13/36 ,  G06F13/40 ,  G06F13/00

CPC classification number: G06F13/4054 ,  G06F13/36

Abstract: A system for transferring data includes structure (i.e, hardware, software, a combination thereof) for requesting data from a second bus, which data is destined for a first bus; and structure for gaining ownership of the second bus for the purpose of transferring the data from the second bus to the first bus, which structure includes substructure for waiting a programmably variable amount of time to see if additional data is requested by the first bus, before relinquishing control of the second bus.

Abstract translation: 用于传送数据的系统包括用于从第二总线请求数据的结构（即，硬件，软件及其组合），哪个数据用于第一总线; 以及为了将数据从第二总线传送到第一总线的目的而获得第二总线的所有权的结构，该结构包括用于等待可编程可变量的时间的子结构，以查看第一总线是否请求附加数据 放弃对二号车的控制。

公开(公告)号：US5859989A

公开(公告)日：1999-01-12

申请号：US855341

申请日：1997-05-13

Applicant: Sompong Paul Olarig ,  Ronald Timothy Horan

Inventor： Sompong Paul Olarig ,  Ronald Timothy Horan

IPC: G06T11/00 ,  G06T13/00

CPC classification number: G06T11/00

Abstract: A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between a 64 bit additional peripheral component interconnect ("PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional PCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional 64 bit PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device utilized on the additional 64 bit PCI bus. Selection of the type of bus bridge (AGP or PCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of a PCI device connected to the common bus.

Abstract translation: 在可以配置为加速图形端口（“AGP”）总线和主机与存储器总线之间的桥接器的计算机系统中提供了多用途核心逻辑芯片组，作为64位附加外围组件互连 “PCI”）总线和主机和存储器总线，或作为主PCI总线和附加PCI总线之间的桥梁。 多个使用芯片组的功能在计算机系统的制造时或在现场确定是否要实现AGP总线桥接器或附加的64位PCI总线桥接器。 多用核心逻辑芯片组具有对在额外的64位PCI总线上使用的每个PCI设备的请求（“REQ”）和Grant（“GNT”）信号线的仲裁器。 在多用途核心逻辑芯片组中选择总线桥（AGP或PCI）的类型可以通过硬件信号输入，或者在计算机系统配置或上电自检（“POST”）期间由软件进行。 在检测到连接到公共总线的PCI设备时也可以确定软件配置。

公开(公告)号：US5852720A

公开(公告)日：1998-12-22

申请号：US695828

申请日：1996-08-16

Applicant: R. Scott Gready ,  Wesley M. Ellinger ,  Gordon R. Clark

Inventor： R. Scott Gready ,  Wesley M. Ellinger ,  Gordon R. Clark

IPC: G06F15/16 ,  G06F11/07 ,  G06F11/273 ,  G06F11/32 ,  G06F11/34 ,  G06F13/00 ,  H04L12/24 ,  H04L29/06

CPC classification number: G06F11/0709 ,  G06F11/0766 ,  G06F11/3466 ,  H04L41/22 ,  H04L67/42 ,  G06F11/2294 ,  G06F11/327 ,  G06F11/3414 ,  G06F11/3476 ,  G06F11/3485 ,  G06F2201/88 ,  H04L41/06

Abstract: A communication system is presented whereby sequences of video screens sent from a host CPU to a video controller can be stored and subsequently retrieved by a terminal located remote from the host CPU. The host CPU and video controller form part of a server arranged within a distributed computing system. An administrator situated at the remote terminal can retrieve select video screens produced during server operations to determine information regarding the server configuration and possible causes of server failure or future failure. The sequence of video screens thereby represent video screen changes stored upon a server controller adapted for coupling to the server expansion bus. The video screen changes represent a sequence of video screen changes occurring prior to server failure or after server reset. Those changes provide beneficial information to an administrator located remote from the server, and allows the administrator to communicate with the server using several possible communication protocols. The server controller snoops display data written from the host CPU to the video controller and mirrors the display data upon buffers within the server controller. Information within the buffers can be called upon by a remotely situated administrator regardless of whether server power is lost in the interim.

Abstract translation: 提供了一种通信系统，其中从主机CPU发送到视频控制器的视频屏幕序列可以被存储并且随后由位于远离主机CPU的终端检索。 主机CPU和视频控制器构成分布式计算系统中安排的服务器的一部分。 位于远程终端的管理员可以检索在服务器操作期间产生的选择视频屏幕，以确定有关服务器配置的信息以及服务器故障或未来故障的可能原因。 因此，视频屏幕的顺序表示存储在适于耦合到服务器扩展总线的服务器控制器上的视频屏幕改变。 视频屏幕更改表示在服务器故障或服务器重置后发生的视频屏幕更改的序列。 这些更改为位于远离服务器的管理员提供有益的信息，并允许管理员使用几种可能的通信协议与服务器进行通信。 服务器控制器将从主机CPU写入的数据显示给视频控制器，并在服务器控制器中的缓冲区上镜像显示数据。 缓冲区内的信息可由远程管理员调用，无论是否在过渡期间服务器功耗丢失。

公开(公告)号：US5821636A

公开(公告)日：1998-10-13

申请号：US907518

申请日：1997-08-08

Applicant: Kenneth R. Baker ,  Kelsey R. Walker

Inventor： Kenneth R. Baker ,  Kelsey R. Walker

IPC: H02J3/38 ,  H02J9/06 ,  H02B1/00

CPC classification number: H02J3/38 ,  H02J9/062 ,  Y10T307/615 ,  Y10T307/647

Abstract: A power distribution system, for use in computer systems and switchable to distribute uninterruptable power received from either of a first or a second power supply, includes a first and a second power input receptacle each being connected to the first and second power supplies respectively. A switch is connected to both the first and the second power input receptacles and is for switching between power received at the first power input receptacle from the first power supply and power received at the second input power receptacle from the second power supply. Two outputs, each with multiple outlet connectors, are connected to the switch and are used for distributing and outputting the power received from either of the first or second power supplies.

Abstract translation: 用于计算机系统并可切换以分配从第一或第二电源中的任一个接收的不间断电力的配电系统包括分别连接到第一和第二电源的第一和第二电力输入插座。 开关连接到第一和第二电源插座两者，并且用于在第一电源输入插座处接收的功率与第一电源之间切换的功率和从第二电源接收的第二输入电源插座处的功率。 两个输出，每个具有多个出口连接器，连接到开关，并用于分配和输出从第一或第二电源中的任一个接收的电力。