公开(公告)号：US20230164995A1

公开(公告)日：2023-05-25

申请号：US17532015

申请日：2021-11-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kosaku YAMASHITA ,  Yasuaki YONEMOCHI

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. An insulating cap layer is formed thereupon. A memory opening is formed, which has a greater lateral dimension at a level of an upper insulating cap sublayer than at a level of a lower insulating cap sublayer. A memory film and a semiconductor channel material layer is formed in the memory opening. Ions of at least one dopant species is implanted into a top portion of the semiconductor channel material layer. An isotropic etch process etches an unimplanted portion of the semiconductor channel material layer at a higher etch rate than the implanted top portion of the semiconductor channel material layer to form a vertical semiconductor channel.

公开(公告)号：US20230164988A1

公开(公告)日：2023-05-25

申请号：US17664550

申请日：2022-05-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/5226

Abstract: A memory device includes at least one instance of a unit layer stack including a source layer, a channel-containing layer that contains a semiconductor channel, and a drain layer that are stacked along a vertical direction over a substrate; a memory opening vertically extending through the at least one instance of the unit layer stack; and a memory opening fill structure located in the memory opening and including a control gate electrode and a memory film in contact with each instance of the semiconductor channel The memory film includes a resonant tunneling barrier stack, a barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the barrier layer.

公开(公告)号：US20230154550A1

公开(公告)日：2023-05-18

申请号：US17529722

申请日：2021-11-18

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Xiang Yang ,  Abhijith Prakash

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/28 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C16/3445 ,  G11C16/3404 ,  G11C16/16 ,  G11C16/28 ,  G11C16/08 ,  G11C16/0433

Abstract: A method of erasing memory cells in a memory device is provided. The method includes grouping a plurality of word lines into a first group, which does not include edge word lines, and a second group, which does include edge word lines. An erase operation is performed on the memory cells of the first and second groups until erase-verify of the memory cells of the first group passes. It is then determined if further erase of the memory cells of the second group is necessary. In response to it being determined that the additional erase operation is necessary, an additional erase operation is performed on at least some of the memory cells of the second group until erase-verify of the memory cells of the second group passes.

公开(公告)号：US20230129421A1

公开(公告)日：2023-04-27

申请号：US17511988

申请日：2021-10-27

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang

IPC: G11C16/34 ,  G11C16/04

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings. Each of the strings has a drain-side select gate transistor on a drain-side connected to one of a plurality of bit lines. A control means is coupled to the word lines and the plurality of bit lines and the drain-side select gate transistors. The control means determines a unique select gate voltage for each of a plurality of groupings of the memory cells that is individually adapted for each of the plurality of groupings. The control means then applies the unique select gate voltage to the drain-side select gate transistor of selected ones of the strings of each of the plurality of groupings of the memory cells to turn on the drain-side select gate transistor of the selected ones of the strings during a memory operation.

公开(公告)号：US20230128682A1

公开(公告)日：2023-04-27

申请号：US18145275

申请日：2022-12-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kartik SONDHI ,  Raghuveer S. MAKALA ,  Adarsh RAJASHEKHAR ,  Rahul SHARANGPANI ,  Fei ZHOU

IPC: H10B41/27 ,  G11C16/04 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory film. The memory film includes a memory material layer having a straight inner cylindrical sidewall that vertically extends through a plurality of electrically conductive layers within the alternating stack without lateral undulation and a laterally-undulating outer sidewall having outward lateral protrusions at levels of the plurality of electrically conductive layers.

公开(公告)号：US20230128177A1

公开(公告)日：2023-04-27

申请号：US17507119

申请日：2021-10-21

Applicant: SanDisk Technologies LLC

Inventor： Ken Oowada ,  Natsu Honda

IPC: G11C16/04 ,  G11C16/14

Abstract: Technology is disclosed for applying a positive temperature coefficient (Tco) voltage to a control terminal of a dummy select transistor. The dummy select transistor resides on a NAND string having non-volatile memory cells and a regular select transistor. The dummy select transistor is typically ON (or conductive) during memory operations such as selected string program, read, and verify. In an aspect, the positive Tco voltage is applied to the control terminal of a dummy select transistor during a program operation. Applying the positive Tco voltage during program operations reduces or eliminates program disturb to the dummy select transistor. In some aspects, the dummy select transistor is used to generate a gate induced drain leakage (GIDL) current during an erase operation. In some aspects, the dummy select transistor is a depletion mode transistor.

公开(公告)号：US20230125748A1

公开(公告)日：2023-04-27

申请号：US17511966

申请日：2021-10-27

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Xiaochen Zhu

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/10 ,  G11C16/28 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control means is coupled to the plurality of word lines and the strings. The control means is configured to apply a primary predetermined voltage to a primary location of the memory apparatus following an erase operation of the memory cells while simultaneously applying a secondary predetermined voltage being lower than the primary predetermined voltage to a secondary location of the memory apparatus and measuring a leak current at the primary location. The control means then determines the erase operation passed in response to the leak current measured not being greater than a predetermined leak threshold.

公开(公告)号：US11631690B2

公开(公告)日：2023-04-18

申请号：US17122296

申请日：2020-12-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Teruo Okina

IPC: H10B43/50 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/522 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11582 ,  H01L27/11573

Abstract: A three-dimensional memory device includes a first three-dimensional memory plane including first alternating stacks of first insulating layers and first word lines, and first bit lines electrically connected first vertical semiconductor channels, and a second three-dimensional memory plane including second alternating stacks of second insulating layers and second word lines and second bit lines electrically connected to second vertical channels. An inter-array backside trench laterally extend between the first three-dimensional memory plane and the second three-dimensional memory plane, and filled with an inter-array backside insulating material portion that provides electrical isolation between the three-dimensional memory planes.

公开(公告)号：US11626496B2

公开(公告)日：2023-04-11

申请号：US17348305

申请日：2021-06-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jun Akaiwa ,  Hiroshi Nakatsuji ,  Masashi Ishida

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/40 ,  H01L29/45 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66

Abstract: A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.

公开(公告)号：US11626418B2

公开(公告)日：2023-04-11

申请号：US17119051

申请日：2020-12-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takeki Ninomiya

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11556 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: A three-dimensional memory device includes an alternating stacks of insulating layers and electrically conductive layers. Memory opening fill structures located in memory openings include a memory film and plural vertical semiconductor channels.