公开(公告)号：US20240039545A1

公开(公告)日：2024-02-01

申请号：US18348899

申请日：2023-07-07

Applicant: STMicroelectronics International N.V.

Inventor： Rupesh SINGH ,  Ankur BAL

IPC: H03L7/195 ,  H03L7/199 ,  H03K3/356

CPC classification number: H03L7/195 ,  H03L7/199 ,  H03K3/356026

Abstract: Provided are a method and apparatus for controlling a skew between multiple data lanes. In the method and apparatus, a first data lane control stage controls control outputting first data over a first data lane based on a first data lane clock and a second data lane control stage controls outputting second data over a second data lane based on a second data lane clock. In the method and apparatus, a first device is associated with a system clock and is configured to generate the first and second data for outputting over the first and second data lanes. A clock control stage causes the first and second data lane clocks to be offset from each other by a fixed time duration that is an integer fraction of a cycle duration of the system clock.

公开(公告)号：US20240039537A1

公开(公告)日：2024-02-01

申请号：US18356146

申请日：2023-07-20

Applicant: STMicroelectronics International N.V.

Inventor： Manoj KUMAR ,  Paras GARG ,  Saiyid Mohammad Irshad RIZVI

IPC: H03K19/003 ,  H03K19/0185

CPC classification number: H03K19/00315 ,  H03K19/018521

Abstract: The present disclosure is directed to a high-voltage fault protection for an interface circuit. The interface circuit is transmitting data signals through an output driver to an external circuit coupled to a PAD contact. The output driver includes pull-up and pull-down drivers. The pull-up driver includes two series PMOS coupled between a voltage supply and the PAD. The pull-down driver includes two series NMOS coupled between the PAD and a ground node. A first safe signal is coupled to one PMOS. A first circuit scheme is designed to generate the first safe signal to be low-logical level voltage when the PAD voltage is lower than a threshold, while being high-logical level voltage when the PAD voltage is higher than the threshold. A second circuit scheme is designed to control one of the series NMOS to be in OFF state when the PAD voltage is higher than the threshold.

公开(公告)号：US20240015945A1

公开(公告)日：2024-01-11

申请号：US18347435

申请日：2023-07-05

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics International N.V.

Inventor： Olivier Weber ,  Kedar Janardan Dhori ,  Promod Kumar ,  Shafquat Jahan Ahmed ,  Christophe Lecocq ,  Pascal Urard

IPC: H10B10/00 ,  G11C11/417

CPC classification number: H10B10/12 ,  H10B10/18 ,  G11C11/417

Abstract: In one embodiment, a semiconductor device includes a carrier substrate, a buried dielectric region overlying the carrier substrate, and a semiconductor film separated from the carrier substrate by the buried dielectric region. NMOS transistors and PMOS transistors are disposed at a surface of the semiconductor film and coupled together to form a static random access memory (SRAM) cell. The NMOS transistors and the PMOS transistors each include a gate dielectric layer having a thickness greater than three nanometers and an active region in the semiconductor film. The active region of the PMOS transistors are formed from a silicon-germanium alloy.

公开(公告)号：US20240012051A1

公开(公告)日：2024-01-11

申请号：US18448265

申请日：2023-08-11

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Shiv Kumar Vats ,  Tripti Gupta

IPC: G01R31/3177 ,  G01R31/317 ,  G06F1/04

CPC classification number: G01R31/3177 ,  G01R31/31724 ,  G01R31/31727 ,  G06F1/04

Abstract: In an embodiment, a method for performing scan includes: entering scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect faults.

公开(公告)号：US20230421101A1

公开(公告)日：2023-12-28

申请号：US18463212

申请日：2023-09-07

Applicant: STMicroelectronics International N.V.

Inventor： Anand KUMAR ,  Nitin JAIN

IPC: H03B5/36

CPC classification number: H03B5/364 ,  H03B2200/0082

Abstract: A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.

公开(公告)号：US11855527B1

公开(公告)日：2023-12-26

申请号：US17834174

申请日：2022-06-07

Applicant: STMicroelectronics International N.V.

Inventor： Ranajay Mallik ,  Akshat Jain

IPC: H02M1/42 ,  H02M1/12 ,  H02M7/217

CPC classification number: H02M1/4216 ,  H02M1/12 ,  H02M1/4225 ,  H02M1/4233 ,  H02M7/2173 ,  H02M7/2176 ,  H02M1/42 ,  H02M7/217

Abstract: A PFC correction circuit includes first, second, and third phase inputs coupled to three-phase power mains, with a three-phase full-wave rectifying bridge connected to an input node. First, second, and third boost inductors are respectively connected between first, second, and third phase inputs and first, second, and third taps of the three-phase full-wave rectifying bridge. A boost switch is connected between the input node and ground, and a boost diode is connected between the input node and an output node. A multiplier input driver generates a single-phase input signal as a replica of a signal at the three-phase power mains after rectification. A single-phase power factor controller generates a PWM signal from the single-phase input signal. A gate driver generates a gate drive signal from the PWM signal. The boost switch is operated by the gate drive signal.

公开(公告)号：US20230412155A1

公开(公告)日：2023-12-21

申请号：US18323998

申请日：2023-05-25

Applicant: STMicroelectronics International N.V.

Inventor： Nitin JAIN ,  Anand KUMAR ,  Kallol CHATTERJEE

IPC: H03K3/03 ,  H03K3/012 ,  H03K3/354

CPC classification number: H03K3/0307 ,  H03K3/3545 ,  H03K3/012

Abstract: A low power crystal oscillator circuit has a high power part and a low power part. Crystal oscillation is initialized using the high power part. An automatic amplitude control circuit includes a current subtractor that decreases current in the high power part as an amplitude of the crystal oscillation increases. A current limiting circuit may limit current in the low power part in order to further reduce power consumption by the low power crystal oscillator circuit. Additionally, an automatic amplitude detection circuit may turn off the high power part after the amplitude of the crystal oscillation reaches a predetermined level in order to further reduce power consumption of the low power crystal oscillator circuit, and may turn back on the high power part after the amplitude of the crystal oscillation reaches a second predetermined level in order to maintain the crystal oscillation.

公开(公告)号：US20230410862A1

公开(公告)日：2023-12-21

申请号：US18136491

申请日：2023-04-19

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C7/16 ,  G11C7/12 ,  G11C8/08

CPC classification number: G11C7/16 ,  G11C8/08 ,  G11C7/12

Abstract: An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by local bit lines. A row controller circuit selectively actuates one word line per sub-array for an in-memory compute operation. A global bit line is capacitively coupled to many local bit lines in either a column direction or row direction. An analog global output voltage on each global bit line is an average of local bit line voltages on the capacitively coupled local bit lines. The analog global output voltage is sampled and converted by an analog-to-digital converter (ADC) circuit to generate a digital decision signal output for the in-memory compute operation.

公开(公告)号：US20230402364A1

公开(公告)日：2023-12-14

申请号：US18451022

申请日：2023-08-16

Applicant: STMicroelectronics International N.V.

Inventor： Luca Maria Carlo DI DIO

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L23/49872 ,  H01L23/49861 ,  H01L21/4846 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49586 ,  H01L23/49582

Abstract: A leadframe including a metal oxide layer on at least a portion of the leadframe are disclosed. More specifically, leadframes with a metal layer and a metal oxide layer formed on one or more leads before a tin finish plating layer is formed are described. The layers of metal and metal oxide between the one or more leads and the tin finish plating layer reduce the formation of tin whiskers, thus reducing the likelihood of shorting and improving the overall reliability of the package structure and device produced.

公开(公告)号：US11836346B2

公开(公告)日：2023-12-05

申请号：US17742987

申请日：2022-05-12

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin Chawla ,  Giuseppe Desoli ,  Anuj Grover ,  Thomas Boesch ,  Surinder Pal Singh ,  Manuj Ayodhyawasi

IPC: G06F3/06 ,  G06N3/08

CPC classification number: G06F3/0604 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0679 ,  G06N3/08

Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.