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    METHODS OF FORMING DIFFUSION BREAKS ON INTEGRATED CIRCUIT PRODUCTS COMPRISED OF FINFET DEVICES AND THE RESULTING PRODUCTS
    151.
    发明申请
    METHODS OF FORMING DIFFUSION BREAKS ON INTEGRATED CIRCUIT PRODUCTS COMPRISED OF FINFET DEVICES AND THE RESULTING PRODUCTS 有权
    在FINFET器件和结果产品所包含的集成电路产品上形成扩散断裂的方法

    公开(公告)号：US20160163604A1

    公开(公告)日：2016-06-09

    申请号：US14674924

    申请日：2015-03-31

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Min Gyu Sung ,  Ryan Ryoung-Han Kim ,  Kwan-Yong Lim ,  Chanro Park

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66

    CPC classification number: H01L21/823878 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: One illustrative method disclosed herein includes forming first sacrificial gate structures above a fin for two active gates and a dummy gate, removing the first sacrificial gate structure for the dummy gate so as to define a cavity that exposes the fin while leaving the first sacrificial gate structures for the two active gates intact, etching through the cavity to form a trench in the fin under the cavity, forming a second sacrificial gate structure for the dummy gate, removing the first sacrificial gate structures for the two active gates and the second sacrificial gate structure for the dummy gate so as to define a replacement gate cavity for the two active gates and the dummy gate, and forming a replacement gate structure in each of the replacement gate cavities, wherein the replacement gate structure for the dummy gate extends into the trench in the fin.

    Abstract translation: 本文公开的一种说明性方法包括在两个有源栅极和伪栅极的鳍片的上方形成第一牺牲栅极结构，去除用于伪栅极的第一牺牲栅极结构，以便限定在离开第一牺牲栅极结构的同时露出鳍片的空腔 对于完整的两个有源栅极，蚀刻通过空腔以在腔下方的鳍形成沟槽，形成用于伪栅极的第二牺牲栅极结构，去除用于两个有源栅极和第二牺牲栅极结构的第一牺牲栅极结构 为了形成用于两个有源栅极和虚拟栅极的替代栅极腔，并且在每个替代栅极腔中形成替代栅极结构，其中用于伪栅极的替代栅极结构延伸到沟槽中 翅膀

    Methods of forming diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products
    152.
    发明授权
    Methods of forming diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products 有权
    在由FinFET器件和所得产品组成的集成电路产品上形成扩散的方法

    公开(公告)号：US09362181B1

    公开(公告)日：2016-06-07

    申请号：US14674924

    申请日：2015-03-31

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Min Gyu Sung ,  Ryan Ryoung-Han Kim ,  Kwan-Yong Lim ,  Chanro Park

    IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

    CPC classification number: H01L21/823878 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: One illustrative method disclosed herein includes forming first sacrificial gate structures above a fin for two active gates and a dummy gate, removing the first sacrificial gate structure for the dummy gate so as to define a cavity that exposes the fin while leaving the first sacrificial gate structures for the two active gates intact, etching through the cavity to form a trench in the fin under the cavity, forming a second sacrificial gate structure for the dummy gate, removing the first sacrificial gate structures for the two active gates and the second sacrificial gate structure for the dummy gate so as to define a replacement gate cavity for the two active gates and the dummy gate, and forming a replacement gate structure in each of the replacement gate cavities, wherein the replacement gate structure for the dummy gate extends into the trench in the fin.

    Abstract translation: 本文公开的一种说明性方法包括在两个有源栅极和伪栅极的鳍片的上方形成第一牺牲栅极结构，去除用于伪栅极的第一牺牲栅极结构，以便限定在离开第一牺牲栅极结构的同时露出鳍片的空腔 对于完整的两个有源栅极，蚀刻通过空腔以在腔下方的鳍形成沟槽，形成用于伪栅极的第二牺牲栅极结构，去除用于两个有源栅极和第二牺牲栅极结构的第一牺牲栅极结构 为了形成用于两个有源栅极和虚拟栅极的替代栅极腔，并且在每个替代栅极腔中形成替代栅极结构，其中用于伪栅极的替代栅极结构延伸到沟槽中 翅膀

    Methods of forming epitaxial semiconductor material in trenches located above the source and drain regions of a semiconductor device
    153.
    发明授权
    Methods of forming epitaxial semiconductor material in trenches located above the source and drain regions of a semiconductor device 有权
    在半导体器件的源极和漏极区域上方的沟槽中形成外延半导体材料的方法

    公开(公告)号：US09312388B2

    公开(公告)日：2016-04-12

    申请号：US14267216

    申请日：2014-05-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Hoon Kim ,  Chanro Park ,  Min Gyu Sung

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08

    CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

    Abstract: One method disclosed includes, among other things, forming a gate structure above an active region of a semiconductor substrate, wherein a first portion of the gate structure is positioned above the active region and second portions of the gate structure are positioned above an isolation region formed in the substrate, forming a sidewall spacer adjacent opposite sides of the first portion of the gate structure so as to define first and second continuous epi formation trenches comprised of the spacer that extend for less than the axial length of the gate structure, and forming an epi semiconductor material on the active region within each of the first and second continuous epi formation trenches.

    Abstract translation: 所公开的一种方法包括在半导体衬底的有源区上方形成栅极结构，其中栅极结构的第一部分位于有源区上方，栅极结构的第二部分位于形成的隔离区的上方 在所述衬底中，形成邻近所述栅极结构的第一部分的相对侧面的侧壁间隔物，以便限定由所述间隔物组成的第一和第二连续外延形成沟槽，所述沟槽延伸小于所述栅极结构的轴向长度，并形成 在第一和第二连续外延形成沟槽的每一个内的有源区域上的外延半导体材料。

    METHODS OF FORMING A PROTECTION LAYER ON A SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE
    155.
    发明申请
    METHODS OF FORMING A PROTECTION LAYER ON A SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE 有权
    在半导体器件和结果器件上形成保护层的方法

    公开(公告)号：US20150364326A1

    公开(公告)日：2015-12-17

    申请号：US14301864

    申请日：2014-06-11

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Chanro Park ,  Xiuyu Cai

    IPC: H01L21/28 ,  H01L29/51

    CPC classification number: H01L29/4232 ,  H01L21/31144 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/78

    Abstract: One illustrative method disclosed herein includes, among other things, forming a first high-k protection layer on the source/drain regions and adjacent the sidewall spacers of a transistor device, removing a sacrificial gate structure positioned between the sidewall spacers so as to thereby define a replacement gate cavity, forming a replacement gate structure in the replacement gate cavity, forming a second high-k protection layer above an upper surface of the spacers, above an upper surface of the replacement gate structure and above the first high-k protection layer, and removing portions of the second high-k protection layer positioned above the first high-k protection layer.

    Abstract translation: 本文公开的一种说明性方法包括在源极/漏极区域上并且邻近晶体管器件的侧壁间隔物处形成第一高k保护层，去除位于侧壁间隔物之间​​的牺牲栅极结构，从而限定 替换栅极腔，在替换栅极腔中形成替代栅极结构，在替代栅极结构的上表面上方并在第一高k保护层上方形成位于间隔物上表面上方的第二高k保护层 以及去除位于第一高k保护层上方的第二高k保护层的部分。

    Airgap spacers formed in conjunction with a late gate cut
    160.
    发明授权
    Airgap spacers formed in conjunction with a late gate cut 有权

    公开(公告)号：US10679894B2

    公开(公告)日：2020-06-09

    申请号：US16185799

    申请日：2018-11-09

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Julien Frougier ,  Ruilong Xie ,  Chanro Park ,  Kangguo Cheng

    IPC: H01L21/768 ,  H01L27/088 ,  H01L29/49 ,  H01L29/66

    Abstract: Methods of forming a field-effect transistor and structures for a field effect-transistor. A sidewall spacer is formed adjacent to a sidewall of a gate structure of the field-effect transistor and a dielectric cap is formed over the gate structure and the sidewall spacer. A cut is formed that extends through the dielectric cap, the gate structure, and the sidewall spacer. After forming the cut, the sidewall spacer is removed from beneath the dielectric cap to define a cavity, and a dielectric material is deposited in the cut and in the cavity. The dielectric material encapsulates a portion of the cavity to define an airgap spacer.

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