公开(公告)号：US20150287614A1

公开(公告)日：2015-10-08

申请号：US14581135

申请日：2014-12-23

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Hong He ,  Ali Khakifirooz ,  Chiahsun Tseng ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L21/321 ,  H01L27/092 ,  H01L21/22 ,  H01L21/8238 ,  H01L29/165

CPC classification number: H01L27/0924 ,  B82Y40/00 ,  H01L21/02236 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A cladding layer is epitaxially grown on a portion of the at least one semiconductor fin. The cladding layer is oxidized such that r such that ions are condensed therefrom and are diffused into the at least one semiconductor fin while the cladding layer is converted to an oxide layer. The oxide layer is removed to expose the at least one semiconductor fin having a diffused fin portion that enhances electron hole mobility therethrough.

Abstract translation: 制造半导体器件的方法包括在半导体衬底上形成至少一个半导体鳍片。 在所述至少一个半导体鳍片的一部分上外延生长覆层。 包覆层被氧化成使得离子从其中冷凝并扩散到至少一个半导体翅片中，同时将包层转化为氧化物层。 去除氧化物层以暴露具有增强电子空穴迁移率的扩散翅片部分的至少一个半导体鳍片。

公开(公告)号：US20150228780A1

公开(公告)日：2015-08-13

申请号：US14174914

申请日：2014-02-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Hong He ,  Ali Khakifirooz ,  Alexander Reznicek ,  Soon-Cheon Seo

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/823412 ,  H01L29/04 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A plurality of semiconductor fins is formed on a surface of an insulator layer. Gate structures are then formed that are orientated perpendicular and straddle each semiconductor fin. A dielectric spacer is then formed on vertical sidewalls of each gate structure. Next, an etch is performed that removes exposed portions of each semiconductor fin and a portion of the insulator layer not protected by the dielectric spacers and the gate structures. The etch provides semiconductor fin portions that have exposed vertical sidewalls. A doped semiconductor material is then formed from each exposed vertical sidewall of each semiconductor fin portion, followed by an anneal which causes diffusion of dopants from the doped semiconductor material into each semiconductor fin portion and the formation of source/drain regions. The source/drain regions are present along the sidewalls of each semiconductor fin portion and are located beneath the dielectric spacers.

Abstract translation: 在绝缘体层的表面上形成多个半导体散热片。 然后形成定向垂直并跨越每个半导体鳍片的栅极结构。 然后在每个栅极结构的垂直侧壁上形成电介质间隔物。 接下来，执行蚀刻，其去除每个半导体鳍片的暴露部分和不被电介质间隔物和栅极结构保护的绝缘体层的一部分。 蚀刻提供具有暴露的垂直侧壁的半导体鳍部分。 然后从每个半导体鳍片部分的每个暴露的垂直侧壁形成掺杂的半导体材料，随后进行退火，其导致掺杂剂从掺杂半导体材料扩散到每个半导体鳍片部分中并形成源极/漏极区域。 源极/漏极区域沿着每个半导体鳍片部分的侧壁存在并且位于电介质间隔物的下方。

公开(公告)号：US20150108572A1

公开(公告)日：2015-04-23

申请号：US14058341

申请日：2013-10-21

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Hong He ,  Chiahsun Tseng ,  Yunpeng Yin

IPC: H01L27/12 ,  H01L21/8234

CPC classification number: H01L21/845 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7831

Abstract: A silicon germanium alloy layer is formed on a semiconductor material layer by epitaxy. An oxygen impermeable layer is formed on the silicon germanium alloy layer. The oxygen impermeable layer and the silicon germanium alloy layer are patterned to form stacks of a silicon germanium alloy fin and an oxygen impermeable cap. A shallow trench isolation structure is formed by deposition, planarization, and recessing or an oxygen permeable dielectric material. An oxygen impermeable spacer is formed around each stack of a silicon germanium alloy fin and an oxygen impermeable cap. A thermal oxidation process is performed to convert a lower portion of each silicon germanium alloy fin into a silicon germanium oxide. During the thermal oxidation process, germanium atoms diffuse into unoxidized portions of the silicon germanium alloy fins to increase the germanium concentration therein.

Abstract translation: 通过外延在半导体材料层上形成硅锗合金层。 在硅锗合金层上形成不透氧层。 对不透氧层和硅锗合金层进行图案化以形成硅锗合金翅片和不透氧盖的叠层。 通过沉积，平坦化和凹陷形成浅沟槽隔离结构或透氧介电材料。 在硅锗合金翅片和不透氧盖的每个堆叠周围形成不透氧隔离物。 进行热氧化处理以将每个硅锗合金翅片的下部转换成硅氧化锗。 在热氧化过程中，锗原子扩散到硅锗合金翅片的未氧化部分，以增加其中的锗浓度。

公开(公告)号：US20150069327A1

公开(公告)日：2015-03-12

申请号：US14023581

申请日：2013-09-11

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Hong He ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L29/15 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L29/158 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/823431 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: FinFET structures may be formed including superlattice fins. The structure may include a superlattice fin of alternating layers of silicon-germanium with a germanium concentration of approximately 10% to 80% and a second semiconductor material. In some embodiments, the second semiconductor material may include either silicon or carbon-doped silicon. Where the second semiconductor material is carbon-doped silicon, the carbon concentration may range from approximately 0.2% to approximately 4%. The superlattice fin may have a height ranging from approximately 5 nm to approximately 100 nm and include between 5 and 30 alternating layers of silicon-germanium and the second semiconductor material. A gate may be formed over the superlattice fin and a source/drain region may be formed over an end of the superlattice fin.

Abstract translation: 可以形成FinFET结构，包括超晶格鳍。 该结构可以包括具有大约10％至80％的锗浓度的硅 - 锗交替层的超晶格鳍和第二半导体材料。 在一些实施例中，第二半导体材料可以包括硅或掺杂碳的硅。 在第二半导体材料是碳掺杂硅的情况下，碳浓度可以在约0.2％至约4％的范围内。 超晶格鳍可以具有约5nm至约100nm的高度，并且包括5至30个硅 - 锗交替层和第二半导体材料。 可以在超晶格鳍上方形成栅极，并且可以在超晶格鳍的端部上形成源极/漏极区域。

公开(公告)号：US08969189B2

公开(公告)日：2015-03-03

申请号：US14027315

申请日：2013-09-16

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/28

CPC classification number: H01L21/28132 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

Abstract: After formation of a replacement gate structure, a template dielectric layer employed to pattern the replacement gate structure is removed. After deposition of a dielectric liner, a first dielectric material layer is deposited by an anisotropic deposition and an isotropic etchback. A second dielectric material layer is deposited and planarized employing the first dielectric material portion as a stopping structure. The first dielectric material portion is removed selective to the second dielectric material layer, and is replaced with gate cap dielectric material portion including at least one dielectric material different from the materials of the dielectric material layers. A contact via hole extending to a source/drain region is formed employing the gate cap dielectric material portion as an etch stop structure. A contact via structure is spaced from the replacement gate structure at least by remaining portions of the gate cap dielectric material portion.

Abstract translation: 在形成替代栅极结构之后，去除用于对置换栅极结构进行图案化的模板电介质层。 在沉积介电衬垫之后，通过各向异性沉积和各向同性回蚀沉积第一介电材料层。 使用第一介电材料部分作为停止结构沉积和平坦化第二电介质材料层。 第一电介质材料部分被选择性地移除到第二电介质材料层，并且被包括不同于介电材料层的材料的至少一种介电材料的栅极盖电介质材料部分代替。 使用栅极绝缘材料部分作为蚀刻停止结构形成延伸到源极/漏极区域的接触孔。 接触通孔结构至少通过栅极盖电介质材料部分的剩余部分与替代栅极结构间隔开。

公开(公告)号：US20150054121A1

公开(公告)日：2015-02-26

申请号：US14035313

申请日：2013-09-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L29/06

CPC classification number: H01L29/0649 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A method for semiconductor fabrication includes patterning one or more mandrels over a semiconductor substrate, the one or more mandrels having dielectric material formed therebetween. A semiconductor layer is formed over exposed portions of the one or more mandrels. A thermal oxidation is performed to diffuse elements from the semiconductor layer into an upper portion of the one or more mandrels and concurrently oxidize a lower portion of the one or more mandrels to form the one or more mandrels on the dielectric material.

Abstract translation: 一种用于半导体制造的方法包括在半导体衬底上图形化一个或多个心轴，所述一个或多个心轴在其间形成介电材料。 在一个或多个心轴的暴露部分上形成半导体层。 执行热氧化以将元件从半导体层扩散到一个或多个心轴的上部，并且同时氧化一个或多个心轴的下部以在电介质材料上形成一个或多个心轴。

公开(公告)号：US08872244B1

公开(公告)日：2014-10-28

申请号：US13865512

申请日：2013-04-18

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/28132 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

Abstract: After formation of a replacement gate structure, a template dielectric layer employed to pattern the replacement gate structure is removed. After deposition of a dielectric liner, a first dielectric material layer is deposited by an anisotropic deposition and an isotropic etchback. A second dielectric material layer is deposited and planarized employing the first dielectric material portion as a stopping structure. The first dielectric material portion is removed selective to the second dielectric material layer, and is replaced with gate cap dielectric material portion including at least one dielectric material different from the materials of the dielectric material layers. A contact via hole extending to a source/drain region is formed employing the gate cap dielectric material portion as an etch stop structure. A contact via structure is spaced from the replacement gate structure at least by remaining portions of the gate cap dielectric material portion.

Abstract translation: 在形成替代栅极结构之后，去除用于对置换栅极结构进行图案化的模板电介质层。 在沉积介电衬垫之后，通过各向异性沉积和各向同性回蚀沉积第一介电材料层。 使用第一介电材料部分作为停止结构沉积和平坦化第二电介质材料层。 第一电介质材料部分被选择性地移除到第二电介质材料层，并且被包括不同于介电材料层的材料的至少一种介电材料的栅极盖电介质材料部分代替。 使用栅极绝缘材料部分作为蚀刻停止结构形成延伸到源极/漏极区域的接触孔。 接触通孔结构至少通过栅极盖电介质材料部分的剩余部分与替代栅极结构间隔开。

公开(公告)号：US20140045324A1

公开(公告)日：2014-02-13

申请号：US14057064

申请日：2013-10-18

Applicant: MATHESON TRI-GAS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Paul D. Brabant ,  Keith Chung ,  Hong He ,  Devendra K. Sadana ,  Manabu Shinriki

IPC: H01L21/02

CPC classification number: H01L21/02532 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02636

Abstract: A high order silane having a formula of SinH2n+2, in which n is an integer greater than 3, in combination with a germanium precursor gas is employed to deposit an epitaxial semiconductor alloy material including at least silicon and germanium on a single crystalline surface. The germanium precursor gas effectively reduces the gas phase reaction of the high order silane, thereby improving the thickness uniformity of the deposited epitaxial semiconductor alloy material. The combination of the high order silane and the germanium precursor gas provides a high deposition rate in the Frank-van der Merwe growth mode for deposition of a single crystalline semiconductor alloy material.

Abstract translation: 使用与锗前体气体组合的具有式SinH2n + 2的其中n为大于3的整数的高级硅烷在单一晶体表面上沉积至少包含硅和锗的外延半导体合金材料。 锗前体气体有效地降低了高级硅烷的气相反应，从而提高了沉积的外延半导体合金材料的厚度均匀性。 高阶硅烷和锗前体气体的组合在用于沉积单晶半导体合金材料的Frank-van der Merwe生长模式中提供高沉积速率。

公开(公告)号：US11201231B2

公开(公告)日：2021-12-14

申请号：US16683979

申请日：2019-11-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Hong He ,  Juntao Li

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  H01L21/18 ,  H01L21/322 ,  H01L21/324

Abstract: A silicon germanium alloy is formed on sidewall surfaces of a silicon fin. An oxidation process or a thermal anneal is employed to convert a portion of the silicon fin into a silicon germanium alloy fin. In some embodiments, the silicon germanium alloy fin has a wide upper portion and a narrower lower portion. In such an embodiment, the wide upper portion has a greater germanium content than the narrower lower portion. In other embodiments, the silicon germanium alloy fin has a narrow upper portion and a wider lower portion. In this embodiment, the narrow upper portion of the silicon germanium alloy fin has a greater germanium content than the wider lower portion of the silicon germanium alloy fin.

公开(公告)号：US10790393B2

公开(公告)日：2020-09-29

申请号：US16267618

申请日：2019-02-05

Applicant: International Business Machines Corporation

Inventor： Andrew M. Greene ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Eric R. Miller ,  Pietro Montanini

IPC: H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66

Abstract: FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).