公开(公告)号：US10217696B2

公开(公告)日：2019-02-26

申请号：US15811198

申请日：2017-11-13

Applicant: International Business Machines Corporation

Inventor： Chiahsun Tseng ,  Jin Liu ,  Lei Zhuang

IPC: H01L21/768 ,  H01L23/48 ,  H01L21/74 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311

Abstract: A first photoresist layer is patterned with a first pattern that includes an opening in a region between areas of two adjacent via holes to be formed. The opening in the first photoresist is transferred into a template layer to form a line trench therein. The lateral dimension of the trench is reduced by depositing a contiguous spacer layer that does not fill the trench completely. An etch-resistant material layer is conformally deposited and fills the trench, and is subsequently recessed to form an etch-resistant material portion filling the trench. A second photoresist layer is applied and patterned with a second pattern, which includes an opening that includes areas of two via holes and an area therebetween. A composite pattern of an intersection of the second pattern and the complement of the pattern of the etch-resistant material portion is transferred through the template layer.

公开(公告)号：US09991255B2

公开(公告)日：2018-06-05

申请号：US14661590

申请日：2015-03-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Renesas Electronics Corporation

Inventor： Hong He ,  Shogo Mochizuki ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L27/088 ,  H01L29/04 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/08

CPC classification number: H01L27/0886 ,  H01L21/02271 ,  H01L21/0257 ,  H01L21/30604 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

Abstract: Semiconductor devices having non-merged fin extensions. A semiconductor device includes fins formed in trenches in an insulator layer, each of the fins having a uniform crystal orientation and a fin cap in a source and drain region that extends vertically and laterally beyond the trench. The fin caps of the respective fins are separate from one another.

公开(公告)号：US20170148790A1

公开(公告)日：2017-05-25

申请号：US15417907

申请日：2017-01-27

Applicant: International Business Machines Corporation

Inventor： Hong HE ,  Siva Kanakasabapathy ,  Yunpeng Yin ,  Chiahsun Tseng ,  Junli Wang

IPC: H01L27/088 ,  H01L21/265 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66795

Abstract: A process for etching a bulk integrated circuit substrate to form features on the substrate, such as fins, having substantially vertical walls comprises forming an etch stop layer beneath the surface of the substrate by ion implantation, e.g., carbon, oxygen, or boron ions or combinations thereof, masking the surface with a patterned etching mask that defines the features by openings in the mask to produce a masked substrate and etching the masked substrate to a level of the etch stop layer to form the features. In silicon substrates, ion implantation takes place along a silicon crystalline lattice beneath the surface of the substrate. The etchant comprises a halogen material that etches undoped silicon faster than the implants-rich silicon layer. This produces a circuit where the fins do not taper away from the vertical where they meet the substrate, and corresponding products and articles of manufacture having these features.

公开(公告)号：US20170040437A1

公开(公告)日：2017-02-09

申请号：US15298828

申请日：2016-10-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Tenko Yamashita ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for semiconductor fabrication includes providing mask layers on opposite sides of a substrate, the substrate having one or more mandrels. Dummy spacers are formed along a periphery of the mask layers. A dummy gate structure is formed between the dummy spacers. The dummy spacers are removed to provide a recess. Low-k spacers are formed in the recess.

Abstract translation: 一种用于半导体制造的方法包括在衬底的相对侧上提供掩模层，所述衬底具有一个或多个心轴。 沿着掩模层的周边形成虚拟间隔物。 在虚拟间隔件之间形成虚拟栅极结构。 去除虚拟间隔物以提供凹陷。 在凹槽中形成低k间隔物。

公开(公告)号：US09543407B2

公开(公告)日：2017-01-10

申请号：US14191751

申请日：2014-02-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Tenko Yamashita ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for semiconductor fabrication includes providing mask layers on opposite sides of a substrate, the substrate having one or more mandrels. Dummy spacers are formed along a periphery of the mask layers. A dummy gate structure is formed between the dummy spacers. The dummy spacers are removed to provide a recess. Low-k spacers are formed in the recess.

Abstract translation: 一种用于半导体制造的方法包括在衬底的相对侧上提供掩模层，所述衬底具有一个或多个心轴。 沿着掩模层的周边形成虚拟间隔物。 在虚拟间隔件之间形成虚拟栅极结构。 去除虚拟间隔物以提供凹陷。 在凹槽中形成低k间隔物。

公开(公告)号：US09484440B2

公开(公告)日：2016-11-01

申请号：US14752095

申请日：2015-06-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Renesas Electronics Corporation

Inventor： Hong He ,  Shogo Mochizuki ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/04 ,  H01L27/088 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L27/0886 ,  H01L21/02271 ,  H01L21/0257 ,  H01L21/30604 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

Abstract: Semiconductor devices having non-merged fin extensions and methods for forming the same. Methods for forming semiconductor devices include forming fins on a substrate; forming a dummy gate over the fins, leaving a source and drain region exposed; etching the fins below a surface level of a surrounding insulator layer; and epitaxially growing fin extensions from the etched fins.

Abstract translation: 具有非合并翅片延伸的半导体器件及其形成方法。 用于形成半导体器件的方法包括在衬底上形成翅片; 在翅片上形成虚拟栅极，留下源极和漏极区域; 在低于周围绝缘体层的表面水平面处蚀刻散热片; 并从蚀刻的翅片外延生长翅片延伸部分。

公开(公告)号：US09391155B2

公开(公告)日：2016-07-12

申请号：US14953908

申请日：2015-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/4966 ,  H01L21/0337 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure includes a dielectric spacer contacting a sidewall of a gate dielectric and a gate conductor. Epitaxial source and drain regions are present on opposing sidewalls of the fin structure, wherein surfaces of the epitaxial source region and the epitaxial drain region that is in contact with the sidewalls of the fin structure are aligned with an outside surface of the dielectric spacer. In some embodiments, the dielectric spacer, the gate dielectric, and the gate conductor of the semiconductor device are formed using a single photoresist mask replacement gate sequence.

公开(公告)号：US09368350B1

公开(公告)日：2016-06-14

申请号：US14747487

申请日：2015-06-23

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chi-Chun Liu ,  Alexander Reznicek ,  Chiahsun Tseng ,  Tenko Yamashita

IPC: H01L21/302 ,  H01L21/033 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/0271 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0338 ,  H01L29/0657

Abstract: A method for DSA fin patterning includes forming a BCP layer over a lithographic stack, the BCP layer having first and second blocks, the lithographic stack disposed over a hard mask and substrate, and the hard mask including first and second dielectric layers; removing the first block to define a fin pattern in the BCP layer with the second block; etching the fin pattern into the first dielectric layer; filling the fin pattern with a tone inversion material; etching back the tone inversion material that overfills the fin pattern; removing the first dielectric layer selectively to define an inverted fin pattern from the tone inversion material; etching the inverted fin pattern into the second dielectric layer of the hard mask; removing the tone inversion material; and transferring the inverted fin pattern of the second dielectric layer into the substrate to define fins.

Abstract translation: 一种用于DSA鳍图形化的方法包括在光刻叠层上形成BCP层，所述BCP层具有第一和第二块，所述光刻堆叠设置在硬掩模和衬底上，并且所述硬掩模包括第一和第二电介质层; 移除所述第一块以在所述BCP层中与所述第二块定义鳍图案; 将鳍状图案蚀刻到第一介电层中; 用色调反转材料填充翅片图案; 蚀刻过度填充鳍图案的色调反转材料; 从所述色调反转材料中选择性地去除所述第一介质层以限定反转的翅片图案; 将倒置的翅片图案蚀刻到硬掩模的第二介电层中; 去除色调反转材料; 并将第二介电层的倒置鳍状图案转印到基板中以限定翅片。

公开(公告)号：US20150287614A1

公开(公告)日：2015-10-08

申请号：US14581135

申请日：2014-12-23

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Hong He ,  Ali Khakifirooz ,  Chiahsun Tseng ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L21/321 ,  H01L27/092 ,  H01L21/22 ,  H01L21/8238 ,  H01L29/165

CPC classification number: H01L27/0924 ,  B82Y40/00 ,  H01L21/02236 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A cladding layer is epitaxially grown on a portion of the at least one semiconductor fin. The cladding layer is oxidized such that r such that ions are condensed therefrom and are diffused into the at least one semiconductor fin while the cladding layer is converted to an oxide layer. The oxide layer is removed to expose the at least one semiconductor fin having a diffused fin portion that enhances electron hole mobility therethrough.

Abstract translation: 制造半导体器件的方法包括在半导体衬底上形成至少一个半导体鳍片。 在所述至少一个半导体鳍片的一部分上外延生长覆层。 包覆层被氧化成使得离子从其中冷凝并扩散到至少一个半导体翅片中，同时将包层转化为氧化物层。 去除氧化物层以暴露具有增强电子空穴迁移率的扩散翅片部分的至少一个半导体鳍片。

公开(公告)号：US20150108572A1

公开(公告)日：2015-04-23

申请号：US14058341

申请日：2013-10-21

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Hong He ,  Chiahsun Tseng ,  Yunpeng Yin

IPC: H01L27/12 ,  H01L21/8234

CPC classification number: H01L21/845 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7831

Abstract: A silicon germanium alloy layer is formed on a semiconductor material layer by epitaxy. An oxygen impermeable layer is formed on the silicon germanium alloy layer. The oxygen impermeable layer and the silicon germanium alloy layer are patterned to form stacks of a silicon germanium alloy fin and an oxygen impermeable cap. A shallow trench isolation structure is formed by deposition, planarization, and recessing or an oxygen permeable dielectric material. An oxygen impermeable spacer is formed around each stack of a silicon germanium alloy fin and an oxygen impermeable cap. A thermal oxidation process is performed to convert a lower portion of each silicon germanium alloy fin into a silicon germanium oxide. During the thermal oxidation process, germanium atoms diffuse into unoxidized portions of the silicon germanium alloy fins to increase the germanium concentration therein.

Abstract translation: 通过外延在半导体材料层上形成硅锗合金层。 在硅锗合金层上形成不透氧层。 对不透氧层和硅锗合金层进行图案化以形成硅锗合金翅片和不透氧盖的叠层。 通过沉积，平坦化和凹陷形成浅沟槽隔离结构或透氧介电材料。 在硅锗合金翅片和不透氧盖的每个堆叠周围形成不透氧隔离物。 进行热氧化处理以将每个硅锗合金翅片的下部转换成硅氧化锗。 在热氧化过程中，锗原子扩散到硅锗合金翅片的未氧化部分，以增加其中的锗浓度。