公开(公告)号：US5186594A

公开(公告)日：1993-02-16

申请号：US511481

申请日：1990-04-19

申请人： Masato M. Toshima ,  Phil M. Salzman ,  Steven C. Murdoch ,  Cheng Wang ,  Mark A. Stenholm ,  James Howard ,  Leonard Hall ,  David Cheng

发明人： Masato M. Toshima ,  Phil M. Salzman ,  Steven C. Murdoch ,  Cheng Wang ,  Mark A. Stenholm ,  James Howard ,  Leonard Hall ,  David Cheng

IPC分类号： H01L21/02 ,  B65G49/05 ,  B65G49/07 ,  B65G65/00 ,  H01L21/205 ,  H01L21/285 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/677

CPC分类号： H01L21/67754 ,  H01L21/67201 ,  H01L21/67766 ,  H01L21/67772 ,  H01L21/67778 ,  Y10S414/137 ,  Y10S414/139 ,  Y10S414/14

摘要： A workpiece loading interface is included within a workpiece processing system which processes workpieces, typically wafers, in a vacuum. The workpiece loading interface includes two separate chambers. Each chamber may be separately pumped down. Thus, while a first cassette of wafers, from a first chamber is being accessed, a second cassette of wafers may be loaded in the second chamber and the second chamber pumped down. Each chamber is designed to minimize intrusion to a clean room. Thus a door to each chamber has a mechanism which, when opening the door, first moves the door slightly away from an opening in the chamber and then the door is moved down parallel to the chamber. After the door is opened, a cassette of wafers is lowered through the opening in a motion much like a drawbridge. The cassette may be pivoted within the chamber when the position from which wafers are accessed from the cassette differs from the position from which the cassette is lowered out of the chamber.

公开(公告)号：USD994819S1

公开(公告)日：2023-08-08

申请号：US29858324

申请日：2022-10-31

申请人： Cheng Wang

设计人： Cheng Wang

摘要： FIG. 1 is a first perspective view of a tent showing my new design;
FIG. 2 is a second perspective view thereof;
FIG. 3 is a front view thereof;
FIG. 4 is a back view thereof
FIG. 5 is a left side view thereof;
FIG. 6 is a right side view thereof;
FIG. 7 is a top view thereof; and,
FIG. 8 is a bottom view thereof.
The broken lines shown in the drawings depict portions of the tent that form no part of the claimed design.

公开(公告)号：US09519467B2

公开(公告)日：2016-12-13

申请号：US13246678

申请日：2011-09-27

申请人： Cheng Wang ,  Youfeng Wu ,  Wei-Yu Chen ,  Bratin Saha ,  Ali Reza Adl-Tabatabai

发明人： Cheng Wang ,  Youfeng Wu ,  Wei-Yu Chen ,  Bratin Saha ,  Ali Reza Adl-Tabatabai

IPC分类号： G06F7/00 ,  G06F17/30 ,  G06F9/45 ,  G06F9/46 ,  G06F9/30

CPC分类号： G06F8/458 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/467

摘要： A method and apparatus for efficient and consistent validation/conflict detection in a Software Transactional Memory (STM) system is herein described. A version check barrier is inserted after a load to compare versions of loaded values before and after the load. In addition, a global timestamp (GTS) is utilized to track a latest committed transaction. Each transaction is associated with a local timestamp (LTS) initialized to the GTS value at the start of a transaction. As a transaction commits it updates the GTS to a new value and sets versions of modified locations to the new value. Pending transactions compare versions determined in read barriers to their LTS. If the version is greater than their LTS indicating another transaction has committed after the pending transaction started and initialized the LTS, then the pending transaction validates its read set to maintain efficient and consistent transactional execution.

摘要翻译： 这里描述了用于在软件事务存储器（STM）系统中有效且一致的验证/冲突检测的方法和装置。 在加载之后插入版本检查障碍，以便在加载之前和之后比较加载值的版本。 此外，使用全局时间戳（GTS）来跟踪最近提交的事务。 每个事务与在事务开始时初始化为GTS值的本地时间戳（LTS）相关联。 作为事务提交，将GTS更新为新值，并将修改的位置的版本设置为新值。 待处理的交易将比较其在LTS阅读障碍中确定的版本。 如果版本大于其LTS，指示在挂起事务启动并初始化LTS之后另一个事务已经提交，则挂起的事务会验证其读取集合以保持有效且一致的事务执行。

公开(公告)号：US20160116964A1

公开(公告)日：2016-04-28

申请号：US14986677

申请日：2016-01-02

申请人： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

发明人： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

IPC分类号： G06F1/32 ,  G06F9/50 ,  G06F9/48 ,  G06F9/38

CPC分类号： G06F1/329 ,  G06F1/3287 ,  G06F9/3851 ,  G06F9/445 ,  G06F9/4893 ,  G06F9/5027 ,  G06F9/5094 ,  G06F11/3409 ,  G06F11/3452 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2209/501 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/34 ,  Y02D50/20

摘要： Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

公开(公告)号：US20160116963A1

公开(公告)日：2016-04-28

申请号：US14986676

申请日：2016-01-02

申请人： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

发明人： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

IPC分类号： G06F1/32 ,  G06F9/50

摘要： Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

摘要翻译： 可以通过在第一处理核上执行程序代码来执行异构多核处理系统上的动态切换核。 可以用信号通知第二处理核心的加电。 可以收集执行程序代码的第一处理核心的第一性能度量。 当第一性能指标优于先前确定的核心性能指标时，可以发信号通知第二处理核心的掉电，并且可以在第一处理核心上继续执行程序代码。 当第一性能度量不比先前确定的核心性能指标更好时，程序代码的执行可以从第一处理核心切换到第二处理核心。

公开(公告)号：US09152417B2

公开(公告)日：2015-10-06

申请号：US13996610

申请日：2011-09-27

申请人： Cheng Wang ,  Youfeng Wu

发明人： Cheng Wang ,  Youfeng Wu

IPC分类号： G06F9/45 ,  G06F9/30 ,  G06F9/455 ,  G06F9/38

CPC分类号： G06F9/30098 ,  G06F8/434 ,  G06F8/4441 ,  G06F9/3834 ,  G06F9/45516

摘要： Embodiments of apparatus, computer-implemented methods, systems, and computer-readable media are described herein for expediting execution time memory alias checking. A sequence of instructions targeted for execution on an execution processor may be received or retrieved. The execution processor may include a plurality of alias registers and circuitry configured to check entries in the alias register for memory aliasing. One or more optimizations may be performed on the received or retrieved sequence of instructions to optimize execution performance of the received or retrieved sequence of instructions. This may include a reorder of a plurality of memory instructions in the received or retrieved sequence of instructions. After the optimization, one or more move instructions may be inserted in the optimized sequence of instructions to move one or more entries among the alias registers during execution, to expedite alias checking at execution time. Other embodiments may be described and/or claimed.

摘要翻译： 本文描述了装置，计算机实现的方法，系统和计算机可读介质的实施例，用于加速执行时间存储器别名检查。 可以接收或检索针对执行处理器执行的指令序列。 执行处理器可以包括多个别名寄存器和被配置为检查别名寄存器中的条目以用于存储器混叠的电路。 可以对所接收或检索的指令序列执行一个或多个优化，以优化所接收或检索的指令序列的执行性能。 这可以包括在接收或检索的指令序列中的多个存储器指令的重排序。 在优化之后，可以在优化的指令序列中插入一个或多个移动指令以在执行期间移动别名寄存器中的一个或多个条目，以在执行时加速别名检查。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20150277866A1

公开(公告)日：2015-10-01

申请号：US14225755

申请日：2014-03-26

申请人： Cheng Wang ,  Youfeng Wu ,  Hongbo Rong ,  Hyunchul Park

发明人： Cheng Wang ,  Youfeng Wu ,  Hongbo Rong ,  Hyunchul Park

IPC分类号： G06F9/45 ,  G06F9/455

CPC分类号： G06F9/45516 ,  G06F9/4411 ,  G06F9/4552 ,  G06F13/10

摘要： In an embodiment, a processor includes at least one core and a dynamic language accelerator to execute a bytecode responsive to a memory mapped input/output (MMIO) operation on a file descriptor associated with the dynamic language accelerator. The processor may block execution of native code while the dynamic language accelerator executes the bytecode. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括至少一个核心和动态语言加速器，以响应于与动态语言加速器相关联的文件描述符的存储器映射的输入/输出（MMIO）操作来执行字节码。 当动态语言加速器执行字节码时，处理器可能会阻止本地代码的执行。 描述和要求保护其他实施例。

公开(公告)号：US09062398B2

公开(公告)日：2015-06-23

申请号：US13326335

申请日：2011-12-15

申请人： Po-Kuei Chou ,  Wei-Yi Yen ,  Din-Sun Ju ,  Tsai-Hsin Cheng ,  Cheng Wang

发明人： Po-Kuei Chou ,  Wei-Yi Yen ,  Din-Sun Ju ,  Tsai-Hsin Cheng ,  Cheng Wang

IPC分类号： B01J7/00 ,  C01B3/08 ,  D04H1/413 ,  D04H1/541

CPC分类号： D04H1/413 ,  D04H1/541 ,  Y02E60/36 ,  Y10T442/641 ,  Y10T442/658

摘要： A non-woven fabric for reacting with a liquid to produce a gas is provided. The non-woven fabric includes at least one non-woven fabric fiber, a plurality of hot melt particles, and a plurality of solid particles. The non-woven fabric fiber has a first melting point. The hot melt particles are bonded with the non-woven fabric fiber and have a second melting point, in which the first melting point is higher than the second melting point. At least a part of the solid particles are bonded with the hot melt particles. Moreover, a method for fabricating the non-woven fabric and a gas generation apparatus using the non-woven fabric are also provided.

摘要翻译： 提供了一种用于与液体反应以产生气体的无纺织物。 无纺布包括至少一种无纺布纤维，多个热熔体颗粒和多个固体颗粒。 无纺布纤维具有第一熔点。 热熔体颗粒与无纺织物纤维结合，具有第二熔点，其中第一熔点高于第二熔点。 至少一部分固体颗粒与热熔体颗粒结合。 此外，还提供了一种制造无纺布的方法和使用该无纺布的气体生成装置。

公开(公告)号：US08960980B2

公开(公告)日：2015-02-24

申请号：US13789683

申请日：2013-03-08

申请人： Han-Wen Tsai ,  Ching-Wei Yu ,  Ming-Feng Kuo ,  Cheng Wang

发明人： Han-Wen Tsai ,  Ching-Wei Yu ,  Ming-Feng Kuo ,  Cheng Wang

IPC分类号： F21V8/00

CPC分类号： G02B6/0008 ,  F21S41/143 ,  F21S41/24 ,  F21S41/26 ,  F21S41/265 ,  G02B6/002 ,  G02B6/0028

摘要： A light source module includes an optical unit, which includes a light-emitting device, a light-guiding device and a light-converging structure. The light-guiding device has a light incident end, a light emitting end, a first curved surface connecting the light incident end and the light emitting end, and a side surface. The light-emitting device is disposed beside the light incident end. The section of the first curved surface by the side surface is a first curve. The section of the first curved surface by the reference plane perpendicular to the side surface is a second curve. The light-converging structure is disposed between the light-emitting device and the light incident end and has a first arc-convex surface and two second convex surfaces, in which the first arc-convex surface and the second convex surfaces are arranged along a direction parallel to the side-surface.

摘要翻译： 光源模块包括光学单元，其包括发光器件，导光器件和聚光结构。 导光装置具有光入射端，发光端，连接光入射端和发光端的第一曲面和侧面。 发光装置设置在光入射端的旁边。 第一曲面由侧面的部分是第一曲线。 第一曲面的垂直于侧面的基准面的截面为第二曲线。 所述聚光结构设置在所述发光元件与所述光入射端之间，具有第一弧形面和第二凸面，所述第一凸出面和所述第二凸面沿着方向 平行于侧面。

公开(公告)号：US20150039861A1

公开(公告)日：2015-02-05

申请号：US14126466

申请日：2013-05-30

申请人： Hongbo Rong ,  Cheng Wang ,  Hyunchul Park ,  Youfeng Wu

发明人： Hongbo Rong ,  Cheng Wang ,  Hyunchul Park ,  Youfeng Wu

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3838 ,  G06F8/434 ,  G06F8/441 ,  G06F8/443 ,  G06F9/30127 ,  G06F9/3017 ,  G06F9/3834 ,  G06F9/384

摘要： In an embodiment, a system includes a processor including one or more cores and a plurality of alias registers to store memory range information associated with a plurality of operations of a loop. The memory range information references one or more memory locations within a memory. The system also includes register assignment means for assigning each of the alias registers to a corresponding operation of the loop, where the assignments are made according to a rotation schedule, and one of the alias registers is assigned to a first operation in a first iteration of the loop and to a second operation in a subsequent iteration of the loop. The system also includes the memory coupled to the processor. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，系统包括处理器，其包括一个或多个核和多个别名寄存器，用于存储与循环的多个操作相关联的存储器范围信息。 存储器范围信息引用存储器内的一个或多个存储器位置。 该系统还包括寄存器分配装置，用于将每个别名寄存器分配给循环的对应操作，其中根据旋转调度进行分配，并且在第一次迭代中将一个别名寄存器分配给第一操作 循环和循环的后续迭代中的第二操作。 该系统还包括耦合到处理器的存储器。 描述和要求保护其他实施例。