公开(公告)号：US20150325627A1

公开(公告)日：2015-11-12

申请号：US14799467

申请日：2015-07-14

Applicant: Micron Technology, Inc.

Inventor： Andrea Redaelli ,  Giorgio Servalli ,  Carmela Cupeta ,  Fabio Pellizzer

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L45/1293 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1675

Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.

Abstract translation: 一些实施例包括形成存储器单元的方法。 加热器结构形成在电节点阵列上，相变材料跨过加热器结构形成。 相变材料被图案化成多个限制结构，其中限制结构与加热器结构一一对应，并且通过一个或多个完全横向围绕每个限制结构的绝缘材料彼此间隔开 。 一些实施例包括在电节点阵列上具有加热器结构的存储器阵列。 密闭相变材料结构在加热器结构之上，并且与加热器结构一一对应。 受限制的相变材料结构通过一个或多个完全横向围绕每个限定相变材料结构的绝缘材料彼此间隔开。

公开(公告)号：US20150243708A1

公开(公告)日：2015-08-27

申请号：US14189490

申请日：2014-02-25

Applicant: MICRON TECHNOLOGY, INC

Inventor： Marcello Ravasio ,  Samuele Sciarrillo ,  Fabio Pellizzer ,  Innocenzo Tortorelli ,  Roberto Somaschini ,  Cristina Casellato ,  Riccardo Mottadelli

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.

Abstract translation: 所公开的技术通常涉及集成电路器件，特别涉及交叉点存储器阵列及其制造方法。 在一个方面，一种制造交叉点存储器阵列的方法包括形成存储单元材料堆，所述存储单元材料堆在第一活性材料上包括第一活性材料和第二活性材料，其中第一和第二活性材料之一包括存储材料 并且第一和第二活性材料中的另一个包括选择材料。 制造交叉点阵列的方法还包括对存储单元材料堆叠进行图案化，其包括通过存储单元材料堆叠的第一和第二活性材料中的至少一个的蚀刻，在至少一个的至少一个的侧壁上形成保护衬垫 在蚀刻通过第一和第二活性材料之一之后蚀刻第一和第二活性材料，并且在第一和第二活性材料之一的侧壁上形成保护衬垫之后进一步蚀刻存储单元材料堆叠。

公开(公告)号：US20150188042A1

公开(公告)日：2015-07-02

申请号：US14642484

申请日：2015-03-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/1253 ,  G11C13/0004 ,  G11C13/003 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141

Abstract: Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the storage component material on approximately vertical walls of the trench and a bottom of the trench. Embodiments may also include etching the storage component material so that at least a portion of the storage component material remains on the approximately vertical walls and the bottom of the trench, wherein the trench is contacting an electrode and a selector such that storage component material on the bottom of the trench contacts the electrode.

Abstract translation: 本文公开的实施例可以包括在介电材料中的和/或沟槽中沉积存储部件材料，包括在沟槽的大致竖直的壁上和沟槽的底部沉积存储部件材料。 实施例还可以包括蚀刻存储部件材料，使得存储部件材料的至少一部分保留在大致垂直的壁和沟槽的底部上，其中沟槽与电极和选择器接触，使得存储部件材料 沟槽底部接触电极。

公开(公告)号：US20150160146A1

公开(公告)日：2015-06-11

申请号：US14596406

申请日：2015-01-14

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli ,  Christina Papagianni ,  Gianpaolo Spadini ,  Jong Won Lee

IPC: G01N27/04

CPC classification number: G01N27/04 ,  H01L22/34 ,  H01L43/10 ,  H01L45/04 ,  H01L45/06 ,  H01L45/14 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

Abstract: Material test structures having cantilever portions and methods of forming the same are described herein. As an example, a method of forming a material test structure includes forming a number of electrode portions in a first dielectric material, forming a second dielectric material on the first dielectric material, wherein the second dielectric material includes a first cantilever portion and a second cantilever portion, and forming a test material on the number of electrode portions, the first dielectric material, and the second dielectric material.

Abstract translation: 本文描述了具有悬臂部分的材料测试结构及其形成方法。 作为示例，形成材料测试结构的方法包括在第一介电材料中形成多个电极部分，在第一电介质材料上形成第二电介质材料，其中第二电介质材料包括第一悬臂部分和第二悬臂 并且在电极部分，第一介电材料和第二介电材料的数量上形成测试材料。

公开(公告)号：US20140339493A1

公开(公告)日：2014-11-20

申请号：US14303652

申请日：2014-06-13

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Hernan A. Castro ,  Eddie T. Flores

IPC: H01L45/00

CPC classification number: H01L45/1273 ,  H01L21/32134 ,  H01L21/76838 ,  H01L27/101 ,  H01L27/2427 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

Abstract: Methods and memory devices formed using etch bias homogenization are provided. One example method of forming a memory device using etch bias homogenization includes forming conductive material at respective levels over a substrate. Each respective level of conductive material is electrically coupled to corresponding circuitry on the substrate during patterning of the respective level of conductive material so that each respective level of conductive material has a homogenized etch bias during patterning thereof. Each respective level of conductive material electrically coupled to corresponding circuitry on the substrate is patterned.

Abstract translation: 提供了使用蚀刻偏压均化形成的方法和存储器件。 使用蚀刻偏压均化形成存储器件的一个示例性方法包括在衬底上形成相应电平的导电材料。 在对相应级别的导电材料进行图案化期间，每个相应级别的导电材料电耦合到衬底上的对应电路，使得每个相应级别的导电材料在其图案化期间具有均质化的蚀刻偏压。 电耦合到衬底上的对应电路的每个相应级别的导电材料被图案化。

公开(公告)号：US20140036583A1

公开(公告)日：2014-02-06

申请号：US14047605

申请日：2013-10-07

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Roberto Bez ,  Ferdinando Bedeschi ,  Roberto Gastaldi

IPC: G11C13/00

CPC classification number: G11C13/0004 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/79 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144

Abstract: A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.

Abstract translation: 一种具有由相变存储元件（3）和选择开关（4）形成的存储单元（2）的相变存储器件。 由自己的相变存储元件（3）和自己的选择开关（4）形成的参考单元（2a）与待读取的存储单元组（7）相关联。 将该组存储器单元的电量与参考单元的类似电量进行比较，由此补偿存储单元的特性中的任何漂移。

公开(公告)号：US12283316B2

公开(公告)日：2025-04-22

申请号：US18409992

申请日：2024-01-11

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer ,  Mattia Robustelli ,  Alessandro Sebastiani

IPC: G11C13/00

Abstract: Methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. Multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. A pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. Pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. Pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. The selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.

公开(公告)号：US12219784B2

公开(公告)日：2025-02-04

申请号：US17431660

申请日：2020-07-22

Applicant: Micron Technology, Inc.

Inventor： Lorenzo Fratin ,  Paolo Fantini ,  Fabio Pellizzer

IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

Abstract: Methods for, apparatuses with and vertical 3D memory devices are described. A vertical 3D memory device may comprise: a plurality of contacts associated with a plurality of digit lines and extending through a substrate; a plurality of word line plates separated from one another by respective dielectric layers and including a first plurality of word line plates and a second plurality of word line plates; a first dielectric material positioned between the first plurality and the second plurality of word line plates, the first dielectric material extending in a serpentine shape over the substrate; a conformal material positioned between the first dielectric material and the first and second plurality of word line plates, respectively; a plurality of spacers; a plurality of pillars coupled with the plurality of contacts; and a plurality of storage elements each comprising chalcogenide material positioned in a recess.

公开(公告)号：US20250037761A1

公开(公告)日：2025-01-30

申请号：US18911720

申请日：2024-10-10

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Lorenzo Fratin ,  Fabio Pellizzer

IPC: G11C13/00 ,  H10B63/00 ,  H10N70/00

Abstract: Methods, systems, and devices for decoding for a memory device are described. A decoder may include a first vertical n-type transistor and a second vertical n-type transistor that extends in a third direction relative to a die of a memory array. The first vertical n-type transistor may be configured to selectively couple an access line with a source node and the second n-type transistor may be configured to selectively couple the access line with a ground node. To activate the access line coupled with the first and second vertical n-type transistors, the first vertical n-type transistor may be activated, the second vertical n-type transistor may be deactivated, and the source node coupled with the first vertical n-type transistor may have a voltage applied that differs from a ground voltage.

公开(公告)号：US12100447B2

公开(公告)日：2024-09-24

申请号：US17864015

申请日：2022-07-13

Applicant: Micron Technology, Inc.

Inventor： Lorenzo Fratin ,  Fabio Pellizzer ,  Agostino Pirovano ,  Russell L. Meyer

IPC: G11C13/00 ,  H01L23/528

CPC classification number: G11C13/0007 ,  G11C13/0026 ,  H01L23/528 ,  G11C2213/71

Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material. Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.