公开(公告)号：US20240313125A1

公开(公告)日：2024-09-19

申请号：US18669237

申请日：2024-05-20

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/66666 ,  H01L29/6675 ,  H01L29/7869

Abstract: A microelectronic device comprises a conductive line and a transistor adjacent to the conductive line. The transistor comprises a channel material extending into the conductive line, the channel material contacting the conductive line in three dimensions, a dielectric material adjacent to the channel material, a conductive material adjacent to the dielectric material, and a passivation material adjacent to the channel material. The microelectronic device further comprises a conductive contact adjacent to the channel material, the conductive contact including a portion extending between opposing portions of the channel material. Related microelectronic devices, electronic devices, and related methods are also disclosed.

公开(公告)号：US12080756B2

公开(公告)日：2024-09-03

申请号：US17647912

申请日：2022-01-13

Applicant: Micron Technology, Inc.

Inventor： Gaurav Musalgaonkar ,  Naveen Kaushik ,  Sonam Jain ,  Haitao Liu ,  Chittoor Ranganathan Parthasarathy

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0626 ,  H01L27/088 ,  H01L29/66681 ,  H01L29/7816

Abstract: An apparatus includes lightly doped drain regions vertically extending into a semiconductor substrate. A channel region is horizontally interposed between the lightly doped drain regions, and source/drain regions vertically extend into the lightly doped drain regions. Breakdown-enhancement implant intrusion regions are within the lightly doped drain regions and are horizontally interposed between the channel region and the source/drain regions. The breakdown enhancement implant regions have a different chemical species than the lightly doped drain regions and have upper boundaries vertically underlying upper boundaries of the lightly doped drain regions. The apparatus also has a gate structure vertically overlying the channel regions and it is horizontally interposed between the breakdown-enhancement implant regions. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US12080331B2

公开(公告)日：2024-09-03

申请号：US18200871

申请日：2023-05-23

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Alessandro Calderoni ,  Richard E Fackenthal ,  Duane R. Mills

IPC: G11C11/404

CPC classification number: G11C11/404

Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage structures and electrically separated from the conductive region.

公开(公告)号：US20240260254A1

公开(公告)日：2024-08-01

申请号：US18403103

申请日：2024-01-03

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Si-Woo Lee ,  Chandra Mouli

IPC: H10B12/00 ,  H01L23/528 ,  H01L29/423

CPC classification number: H10B12/33 ,  H01L23/5283 ,  H01L29/42392 ,  H10B12/03 ,  H10B12/482 ,  H10B12/488

Abstract: Methods, apparatuses, and systems related to a memory device having transistor body contacts that extend vertically across stacked circuit layers and connect to body portions of data access transistors are described. A memory device may include storage cells and corresponding access circuits on each of the stacked layers. The vertically extending transistor body contacts may provide a route for leakage away from data storage circuits when the data access transistors are off.

公开(公告)号：US20240251543A1

公开(公告)日：2024-07-25

申请号：US18623929

申请日：2024-04-01

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy

IPC: H10B12/00 ,  G11C5/06 ,  H01L29/24

CPC classification number: H10B12/20 ,  G11C5/063 ,  H01L29/24 ,  H10B12/01

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a conductive region, a first data line, a second data line, a first memory cell coupled to the first data line and the conductive region, a second memory cell coupled to the second data line and the conductive region, a conductive structure, and a conductive line. The first memory cell includes a first transistor coupled to a second transistor, the first transistor including a first charge storage structure. The second memory cell includes a third transistor coupled to a fourth transistor, the third transistor including a second charge storage structure. The conductive structure is located between and electrically separated from the first and second charge storage structures. The conductive line forms a gate of each of the first, second, third, and fourth transistors.

公开(公告)号：US12040411B2

公开(公告)日：2024-07-16

申请号：US17446362

申请日：2021-08-30

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78696 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/823412 ,  H01L29/66666 ,  H01L29/66969 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/7869

Abstract: A device comprises a first conductive line and a vertical transistor over the first conductive line. The vertical transistor comprises a gate electrode, a gate dielectric material overlying sides of the gate electrode, and a channel region on sides of the gate dielectric material, the gate dielectric material located between the channel region and the gate electrode. The device further comprises a second conductive line overlying a conductive contact of the at least one vertical transistor. Related devices and methods of forming the devices are also disclosed.

公开(公告)号：US20240234311A1

公开(公告)日：2024-07-11

申请号：US18610267

申请日：2024-03-20

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Haitao Liu ,  Vladimir Mikhalev

IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L23/528 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/66666 ,  H01L29/78 ,  H01L29/7827 ,  H10B10/12

Abstract: A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.

公开(公告)号：US20240188274A1

公开(公告)日：2024-06-06

申请号：US18523069

申请日：2023-11-29

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Durai Vishak Nirmal Ramaswamy ,  Karthik Sarpatwari ,  Haitao Liu

IPC: H10B12/00 ,  G11C11/405 ,  G11C11/4096

CPC classification number: H10B12/00 ,  G11C11/405 ,  G11C11/4096

Abstract: Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes a first conductive structure, a second conductive structure, a conductive portion coupled to one of the conductive structures, and a memory cell. The memory cell includes different semiconductor portions located on different levels of the apparatus and separated from each other by a dielectric portion. The first semiconductor portion is coupled to the first and second conductive structures. The second semiconductor portion is coupled to the first conductive structure. The memory cell includes a charge storage structure coupled to the second semiconductor portion. The charge storage structure includes multiple portions. Part of the conductive portion is located between portions of the charge storage structure and separated from the charge storage structure by a dielectric material.

公开(公告)号：US11935960B2

公开(公告)日：2024-03-19

申请号：US17864244

申请日：2022-07-13

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Litao Yang ,  Haitao Liu ,  Kamal M. Karda

IPC: H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H10B12/00 ,  H10B53/20

CPC classification number: H01L29/78642 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7869 ,  H10B12/31 ,  H10B53/20

Abstract: Some embodiments include integrated memory. The integrated memory includes a first series of first conductive structures and a second series of conductive structures. The first conductive structures extend along a first direction. The second conductive structures extend along a second direction which crosses the first direction. Pillars of semiconductor material extend upwardly from the first conductive structures. Each of the pillars includes a lower source/drain region, an upper source/drain region, and a channel region between the lower and upper source/drain regions. The lower source/drain regions are coupled with the first conductive structures. Insulative material is adjacent sidewall surfaces of the pillars. The insulative material includes ZrOx, where x is a number greater than 0. The second conductive structures include gating regions which are spaced from the channel regions by at least the insulative material. Storage elements are coupled with the upper source/drain regions.

公开(公告)号：US20240064966A1

公开(公告)日：2024-02-22

申请号：US17891790

申请日：2022-08-19

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Litao Yang ,  Haitao Liu ,  Si-Woo Lee

IPC: H01L27/108 ,  G11C11/22

CPC classification number: H01L27/10826 ,  G11C11/221 ,  H01L27/10882

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells. The vertically stacked memory cells have horizontally oriented access devices having a first source/drain region, a channel region, and a second source drain and horizontally oriented storage nodes that are vertically separated from the access devices. Horizontally oriented access lines are coupled to gates, separated from the respective channel regions by gate dielectrics, and vertically oriented digit lines are coupled to respective first source/drain regions. The horizontally oriented storage nodes each have a first electrode coupled to the second source/drain regions of the access devices and each first electrode opposes two different sides of the horizontal access devices including an electrical contact with a vertical side of the second source/drain regions.