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    Arrays Of Nonvolatile Memory Cells And Methods Of Forming Arrays Of Nonvolatile Memory Cells
    151.
    发明申请
    Arrays Of Nonvolatile Memory Cells And Methods Of Forming Arrays Of Nonvolatile Memory Cells 有权
    非易失性存储器单元的阵列和形成非易失性存储器单元阵列的方法

    公开(公告)号：US20130329479A1

    公开(公告)日：2013-12-12

    申请号：US13970369

    申请日：2013-08-19

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu

    IPC: G11C5/02 ,  H01L21/302

    CPC classification number: H01L45/1608 ,  G11C5/02 ,  G11C5/06 ,  G11C13/0004 ,  G11C2213/71 ,  H01L21/302 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/165

    Abstract: An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first plurality of horizontally oriented first electrode lines and a second plurality of horizontally oriented second electrode lines crossing relative to the first electrode lines. Individual of the memory cells include a crossing one of the first electrode lines and one of the second electrode lines and material there-between. Specifically, programmable material, a select device in series with the programmable material, and current conductive material in series between and with the programmable material and the select device are provided in series with such crossing ones of the first and second electrode lines. The material and devices may be oriented for predominant current flow in defined horizontal and vertical directions. Method and other implementations and aspects are disclosed.

    Abstract translation: 非易失性存储单元的阵列包括多个垂直堆叠的非易失性存储单元层。 层分别包括第一多个水平取向的第一电极线和相对于第一电极线交叉的第二多个水平取向的第二电极线。 存储单元的个体包括第一电极线和第二电极线中的一个之间的交叉的一个以及其间的材料。 具体地说，与可编程材料串联的选择装置以及与可编程材料和选择装置之间串联的当前导电材料与第一和第二电极线中交叉的那些串联地提供。 材料和装置可以被定向成在限定的水平和垂直方向上的主要电流流动。 公开了方法和其他实现和方面。

    Memory Cells, Methods of Forming Memory Cells, and Methods of Programming Memory Cells
    153.
    发明申请
    Memory Cells, Methods of Forming Memory Cells, and Methods of Programming Memory Cells 有权
    记忆细胞，形成记忆细胞的方法和编程记忆细胞的方法

    公开(公告)号：US20130279239A1

    公开(公告)日：2013-10-24

    申请号：US13919677

    申请日：2013-06-17

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Gurtej S. Sandhu

    IPC: G11C13/00 ,  H01L45/00

    CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C2013/0073 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/145 ,  H01L45/1608 ,  H01L45/165

    Abstract: Some embodiments include methods in which a memory cell is formed to have programmable material between first and second access lines, with the programmable material having two compositionally different regions. A concentration of ions and/or ion-vacancies may be altered in at least one of the regions to change a memory state of the memory cell and to simultaneously form a pn diode. Some embodiments include memory cells having programmable material with two compositionally different regions, and having ions and/or ion-vacancies diffusible into at least one of the regions. The memory cell has a memory state in which the first and second regions are of opposite conductivity type relative to one another.

    Abstract translation: 一些实施例包括其中存储单元形成为在第一和第二访问线之间具有可编程材料的方法，其中可编程材料具有两个组成上不同的区域。 可以在至少一个区域中改变离子和/或离子空位的浓度以改变存储器单元的存储状态并同时形成pn二极管。 一些实施例包括具有两个组成不同区域的可编程材料并且具有可扩散到至少一个区域中的离子和/或离子空位的存储器单元。 存储单元具有其中第一和第二区域相对于彼此具有相反导电类型的存储状态。

    Memory Devices and Formation Methods
    154.
    发明申请
    Memory Devices and Formation Methods 有权
    存储器件和形成方法

    公开(公告)号：US20130240819A1

    公开(公告)日：2013-09-19

    申请号：US13888674

    申请日：2013-05-07

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jun Liu ,  Gurtej S. Sandhu

    IPC: H01L45/00

    CPC classification number: H01L21/02225 ,  H01L27/2409 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/16

    Abstract: A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types. After activating the dopant, the substrate is bonded to the insulator material and at least some of the substrate is removed where bonded to the insulator material. After the removing, a memory cell is formed having a word line, an access diode, a state-changeable memory element containing chalcogenide phase change material, and a bit line all electrically connected in series, the access diode containing the junction as a p-n junction. A memory device includes an adhesion material over the insulator material and bonding the word line to the insulator material.

    Abstract translation: 一种方法包括在具有含金属的导电互连的集成电路上形成电绝缘体材料，并激活衬底的半导体材料中的掺杂剂以提供掺杂区域。 掺杂区域提供相反导电类型的结。 在激活掺杂剂之后，衬底被结合到绝缘体材料上，并且至少部分衬底在与绝缘体材料接合的情况下被去除。 在移除之后，形成具有字线，存取二极管，含有硫族化物相变材料的状态可变存储元件和全部电连接的位线的存储单元，该存储二极管包含该结作为pn结 。 存储器件包括绝缘体材料上的粘合材料并将字线连接到绝缘体材料上。

    Semiconductor devices and related methods
    156.
    发明授权
    Semiconductor devices and related methods 有权

    公开(公告)号：US11316107B2

    公开(公告)日：2022-04-26

    申请号：US16876693

    申请日：2020-05-18

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Kunal R. Parekh

    IPC: H01L45/00 ,  H01L27/24 ,  H01L21/033 ,  H01L21/768 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

    Abstract: Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.

    Methods for forming narrow vertical pillars and integrated circuit devices having the same
    157.
    发明授权
    Methods for forming narrow vertical pillars and integrated circuit devices having the same 有权

    公开(公告)号：US10971683B2

    公开(公告)日：2021-04-06

    申请号：US16934844

    申请日：2020-07-21

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Kunal Parekh

    IPC: H01L45/00 ,  H01L27/24

    Abstract: In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.

    Memory Cells, Memory Cell Programming Methods, Memory Cell Reading Methods, Memory Cell Operating Methods, and Memory Devices
    158.
    发明申请
    Memory Cells, Memory Cell Programming Methods, Memory Cell Reading Methods, Memory Cell Operating Methods, and Memory Devices 有权

    公开(公告)号：US20210005259A1

    公开(公告)日：2021-01-07

    申请号：US17031454

    申请日：2020-09-24

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu

    IPC: G11C13/00

    Abstract: Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.

    Methods for forming narrow vertical pillars and integrated circuit devices having the same
    159.
    发明授权
    Methods for forming narrow vertical pillars and integrated circuit devices having the same 有权

    公开(公告)号：US10756265B2

    公开(公告)日：2020-08-25

    申请号：US16185161

    申请日：2018-11-09

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Kunal Parekh

    IPC: H01L45/00 ,  H01L27/24

    Abstract: In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.

    Semiconductor devices and related methods
    160.
    发明授权
    Semiconductor devices and related methods 有权

    公开(公告)号：US10700279B2

    公开(公告)日：2020-06-30

    申请号：US16200969

    申请日：2018-11-27

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Kunal R. Parekh

    IPC: H01L45/00 ,  H01L43/02 ,  H01L27/24 ,  H01L21/033 ,  H01L21/768 ,  H01L43/08 ,  H01L43/12

    Abstract: Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.

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