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    MEMORY HAVING A CONTINUOUS CHANNEL
    155.
    发明申请
    MEMORY HAVING A CONTINUOUS CHANNEL 有权
    具有连续通道的记忆

    公开(公告)号：US20160099252A1

    公开(公告)日：2016-04-07

    申请号：US14831011

    申请日：2015-08-20

    Applicant: Micron Technology, Inc.

    Inventor： Luan C. Tran ,  Hongbin Zhu ,  John D. Hopkins ,  Yushi Hu

    IPC: H01L27/115

    CPC classification number: H01L27/11556 ,  H01L21/823412 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/11582 ,  H01L29/7827

    Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.

    Abstract translation: 本公开包括具有连续信道的存储器及其处理方法。 许多实施例包括形成具有串联连接在源选择栅极和漏极选择栅极之间的存储单元的垂直堆叠，其中形成垂直堆叠包括形成用于源选择栅极，存储器单元和漏极选择的连续沟道 栅极，并且去除用于漏极选择栅极的连续沟道的一部分，使得连续沟道对于漏极选择栅极比对于存储器单元和源选择栅极更薄。

    Memory Arrays
    156.
    发明申请
    Memory Arrays 有权
    记忆阵列

    公开(公告)号：US20150333143A1

    公开(公告)日：2015-11-19

    申请号：US14281569

    申请日：2014-05-19

    Applicant: Micron Technology, Inc.

    Inventor： John M. Meldrim ,  Yushi Hu ,  Rita J. Klein ,  John D. Hopkins ,  Hongbin Zhu ,  Gordon A. Haller ,  Luan C. Tran

    IPC: H01L29/49 ,  H01L21/28 ,  H01L27/115

    CPC classification number: H01L27/11582 ,  H01L21/28097 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4975

    Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

    Abstract translation: 一些实施例包括具有交替的第一和第二电平的堆叠的存储器阵列。 通道材料柱延伸通过堆叠，并且垂直堆叠的存储器单元串沿着通道材料柱。 一个共同的来源在堆叠下，并且电耦合到通道材料柱。 普通源在金属硅化物上方具有导电保护材料，并且直接抵抗金属硅化物，导电保护材料是金属硅化物以外的组合物。 一些实施例包括制造集成结构的方法。

    Patterned Bases, and Patterning Methods
    157.
    发明申请
    Patterned Bases, and Patterning Methods 有权
    图案基础和图案化方法

    公开(公告)号：US20150076663A1

    公开(公告)日：2015-03-19

    申请号：US14548004

    申请日：2014-11-19

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins

    IPC: H01L21/308 ,  H01L29/06 ,  H01L21/033

    CPC classification number: H01L21/3086 ,  G03F7/0035 ,  H01L21/0337 ,  H01L21/3088 ,  H01L27/10894 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/0657

    Abstract: Some embodiments include methods of patterning a base. First and second masking features are formed over the base. The first and second masking features include pedestals of carbon-containing material capped with silicon oxynitride. A mask is formed over the second masking features, and the silicon oxynitride caps are removed from the first masking features. Spacers are formed along sidewalls of the first masking features. The mask and the carbon-containing material of the first masking features are removed. Patterns of the spacers and second masking features are transferred into one or more materials of the base to pattern said one or more materials. Some embodiments include patterned bases.

    Abstract translation: 一些实施例包括图案化基底的方法。 在基底上形成第一和第二掩蔽特征。 第一和第二掩模特征包括用氮氧化硅覆盖的含碳材料的基座。 在第二掩蔽特征上形成掩模，并且从第一掩蔽特征中去除氧氮化硅帽。 间隔件沿着第一掩蔽特征的侧壁形成。 去除掩模和第一掩蔽特征的含碳材料。 间隔物和第二掩蔽特征的图案被转移到基底的一种或多种材料中以图案化所述一种或多种材料。 一些实施例包括图案化基底。

    Patterned Semiconductor Bases, and Patterning Methods
    158.
    发明申请
    Patterned Semiconductor Bases, and Patterning Methods 有权
    图案化半导体基板和图案化方法

    公开(公告)号：US20130161799A1

    公开(公告)日：2013-06-27

    申请号：US13769461

    申请日：2013-02-18

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins

    IPC: H01L29/02

    CPC classification number: H01L21/0337 ,  H01L21/3086 ,  H01L21/3088 ,  H01L27/10894 ,  H01L27/11526 ,  H01L27/11573

    Abstract: Some embodiments include patterning methods. First and second masking features may be formed over first and second regions of a semiconductor base, respectively. A protective mask may be formed over the second masking features. First and second spacers may be formed along sidewall edges of the first masking features and along lateral edges of the protective mask, respectively. The protective mask and the first masking features may be removed without removing the second masking features, without removing the first spacers, and without removing the second spacers. The first spacers may be third masking features that are at a tighter pitch than the first masking features. Patterns of the second masking features and the third masking features may be transferred into the semiconductor base. Some embodiments include patterned semiconductor bases.

    Abstract translation: 一些实施方案包括图案化方法。 第一和第二掩蔽特征可以分别形成在半导体基底的第一和第二区域上。 可以在第二掩蔽特征上形成保护掩模。 第一和第二间隔物可以分别沿着第一掩蔽特征的侧壁边缘和沿防护罩的侧边缘形成。 可以在不移除第二掩蔽特征的情况下去除保护掩模和第一掩蔽特征，而不去除第一间隔物，并且不移除第二间隔物。 第一间隔物可以是比第一掩蔽特征更紧的间距的第三掩蔽特征。 可以将第二掩蔽特征和第三掩蔽特征的图案转移到半导体基底中。 一些实施例包括图案化的半导体基底。

    Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
    159.
    发明授权
    Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells 有权

    公开(公告)号：US12300318B2

    公开(公告)日：2025-05-13

    申请号：US17727515

    申请日：2022-04-22

    Applicant: Micron Technology, Inc.

    Inventor： Alyssa N. Scarbrough ,  Jordan D. Greenlee ,  John D. Hopkins

    IPC: H01L23/528 ,  G11C16/04 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. Below the stack, an insulating tier is directly above the conductor tier and a metal-material tier is directly above the insulating tier. Conductive rings extend through the metal-material tier and the insulating tier to conductor material of the conductor tier. The conductive rings individually are around individual horizontal locations directly above which are individual of the channel-material strings. The channel-material strings directly electrically couple to the conductor material of the conductor tier through the insulating tier by the conductive rings. Other embodiments, including method, are disclosed.

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