公开(公告)号：US20190355592A1

公开(公告)日：2019-11-21

申请号：US16526375

申请日：2019-07-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Junichiro SAKATA ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Miyuki HOSOBA ,  Masayuki SAKAKURA ,  Yoshiaki OIKAWA

IPC: H01L21/477 ,  H01L29/786 ,  H01L27/12 ,  H01L21/02 ,  G02F1/1368 ,  G02F1/1333 ,  H01L29/66

Abstract: An object is to provide a display device with excellent display characteristics, where a pixel circuit and a driver circuit provided over one substrate are formed using transistors which have different structures corresponding to characteristics of the respective circuits. The driver circuit portion includes a driver circuit transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using a metal film, and a channel layer is formed using an oxide semiconductor. The pixel portion includes a pixel transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using an oxide conductor, and a semiconductor layer is formed using an oxide semiconductor. The pixel transistor is formed using a light-transmitting material, and thus, a display device with higher aperture ratio can be manufactured.

公开(公告)号：US20190312063A1

公开(公告)日：2019-10-10

申请号：US16435966

申请日：2019-06-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Atsushi HIROSE ,  Masashi TSUBUKU ,  Kosei NODA

IPC: H01L27/12 ,  H04R1/02 ,  H01L33/02 ,  H04M1/02 ,  H01L27/15 ,  H01L27/32 ,  H01L29/786 ,  H01L29/24 ,  H01L29/36

Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.

公开(公告)号：US20190088793A1

公开(公告)日：2019-03-21

申请号：US16191609

申请日：2018-11-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hajime KIMURA ,  Kengo AKIMOTO ,  Masashi TSUBUKU ,  Toshinari SASAKI

IPC: H01L29/786 ,  G09G3/36 ,  H01L27/12

Abstract: A display device including a pixel having a memory. The pixel includes at least a display element, a capacitor, an inverter, and a switch. The switch is controlled with a signal held in the capacitor and a signal output from the inverter so that voltage is supplied to the display element. The inverter and the switch can be constituted by transistors with the same polarity. A semiconductor layer included in the pixel may be formed using a light-transmitting material. Moreover, a gate electrode, a drain electrode, and a capacitor electrode may be formed using a light-transmitting conductive layer. The pixel is formed using a light-transmitting material in such a manner, whereby the display device can be a transmissive display device while including a pixel having a memory.

公开(公告)号：US20180364510A1

公开(公告)日：2018-12-20

申请号：US16109886

申请日：2018-08-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Hiroyuki MIYAKE ,  Masashi TSUBUKU ,  Kosei NODA

IPC: G02F1/1368 ,  H01L29/786 ,  H01L27/12 ,  G09G3/36

CPC classification number: G02F1/1368 ,  G09G3/3611 ,  G09G3/3648 ,  G09G3/3674 ,  G09G3/3677 ,  G09G5/18 ,  G09G2310/0286 ,  G09G2320/103 ,  G09G2330/021 ,  G09G2330/022 ,  G09G2330/027 ,  H01L27/1225 ,  H01L29/7869

Abstract: A liquid crystal display device includes: a driver circuit portion; a pixel portion; a signal generation circuit for generating a control signal for driving the driver circuit portion and an image signal which is supplied to the pixel portion; a memory circuit; a comparison circuit for detecting a difference of image signals for a series of frame periods among image signals stored for respective frame periods in the memory circuit; a selection circuit which selects and outputs the image signals for the series of frame periods when the difference is detected in the comparison circuit; and a display control circuit which supplies the control signal and the image signals output from the selection circuit, to the driver circuit portion when the difference is detected in the comparison circuit, and stops supplying the control signal to the driver circuit portion when the difference is not detected in the comparison circuit.

公开(公告)号：US20180337289A1

公开(公告)日：2018-11-22

申请号：US16034456

申请日：2018-07-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kenichi OKAZAKI ,  Masashi TSUBUKU ,  Satoru SAITO ,  Noritaka ISHIHARA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/04 ,  H01L29/24

CPC classification number: H01L29/78696 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/24 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor device with improved electrical characteristics is provided. A semiconductor device with improved field effect mobility is provided. A semiconductor device in which the field-effect mobility is not lowered even at high temperatures is provided. A semiconductor device which can be formed at low temperatures is provided. A semiconductor device with improved productivity can be provided. In the semiconductor device, there is a range of a gate voltage where the field-effect mobility increases as the temperature increases within a range of the gate voltage from 0 V to 10 V. For example, such a range of a gate voltage exists at temperatures ranging from a room temperature (25° C.) to 120° C. In the semiconductor device, the off-state current is kept extremely low (lower than or equal to the detection limit of a measurement device) within the above temperature range.

公开(公告)号：US20180301476A1

公开(公告)日：2018-10-18

申请号：US16008437

申请日：2018-06-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Masashi TSUBUKU ,  Kosei NODA

IPC: H01L27/12 ,  H03K19/096 ,  G09G3/20 ,  H03K17/16 ,  H01L29/786 ,  G11C19/28 ,  G11C19/18 ,  H03K19/003 ,  G09G3/3291 ,  G09G3/36 ,  G09G3/3233

Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10−13A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

公开(公告)号：US20170352746A1

公开(公告)日：2017-12-07

申请号：US15664106

申请日：2017-07-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Akihisa SHIMOMURA ,  Yasumasa YAMANE ,  Yuhei SATO ,  Tetsuhiro TANAKA ,  Masashi TSUBUKU ,  Toshihiko TAKEUCHI ,  Ryo TOKUMARU ,  Mitsuhiro ICHIJO ,  Satoshi TORIUMI ,  Takashi OHTSUKI ,  Toshiya ENDO

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved. Oxygen is introduced into a surface of an insulating film, and then, an oxide semiconductor, a layer which is capable of blocking oxygen, a gate insulating film, and other films which composes a transistor are formed. For at least one of the first gate insulating film and the insulating film, three signals in Electron Spin Resonance Measurement are each observed in a certain range of g-factor. Reducing the sum of the spin densities of the signals will improve reliability of the semiconductor device.

公开(公告)号：US20170301796A1

公开(公告)日：2017-10-19

申请号：US15634167

申请日：2017-06-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Noritaka ISHIHARA ,  Masashi OOTA ,  Masashi TSUBUKU ,  Masami JINTYOU ,  Yukinori SHIMA ,  Junichi KOEZUKA ,  Yasuharu HOSAKA ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/45 ,  H01L29/04 ,  H01L29/24 ,  H01L29/423 ,  H01L27/12

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/04 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78693 ,  H01L29/78696

Abstract: Defects in an oxide semiconductor film are reduced in a semiconductor device including the oxide semiconductor film. The electrical characteristics of a semiconductor device including an oxide semiconductor film are improved. The reliability of a semiconductor device including an oxide semiconductor film is improved. A semiconductor device including an oxide semiconductor layer; a metal oxide layer in contact with the oxide semiconductor layer, the metal oxide layer including an In-M oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, or Hf); and a conductive layer in contact with the metal oxide layer, the conductive layer including copper, aluminum, gold, or silver is provided. In the semiconductor device, y/(x+y) is greater than or equal to 0.75 and less than 1 where the atomic ratio of In to M included in the metal oxide layer is In:M=x:y.

公开(公告)号：US20170263777A1

公开(公告)日：2017-09-14

申请号：US15609513

申请日：2017-05-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Hiroyuki MIYAKE ,  Kei TAKAHASHI ,  Kouhei TOYOTAKA ,  Masashi TSUBUKU ,  Kosei NODA ,  Hideaki KUWABARA

IPC: H01L29/786 ,  H01L23/552 ,  H01L23/66 ,  H01L49/02 ,  H01L27/02 ,  H01L27/108 ,  H01L27/12 ,  H01L21/84 ,  H01L25/16

CPC classification number: H01L29/7869 ,  H01L21/84 ,  H01L23/552 ,  H01L23/60 ,  H01L23/66 ,  H01L25/16 ,  H01L27/0222 ,  H01L27/10873 ,  H01L27/12 ,  H01L27/1225 ,  H01L28/20 ,  H01L28/60 ,  H01L29/78609 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit included in an LSI, a CPU, or a memory is manufactured using the transistor which is formed using an oxide semiconductor which is an intrinsic or substantially intrinsic semiconductor obtained by removal of impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than a silicon semiconductor, and is formed over a semiconductor substrate. With the transistor which is formed over the semiconductor substrate and includes the highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device whose power consumption due to leakage current is low can be realized.

公开(公告)号：US20170229563A1

公开(公告)日：2017-08-10

申请号：US15498782

申请日：2017-04-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Hitoshi NAKAYAMA ,  Masashi TSUBUKU ,  Daigo SHIMADA

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/66 ,  H01L27/12

CPC classification number: H01L29/66969 ,  H01L22/14 ,  H01L27/088 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/7869

Abstract: When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.