公开(公告)号：US20240375236A1

公开(公告)日：2024-11-14

申请号：US18783920

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Wei Chang ,  Ming-Fa Chen ,  Chao-Wen Shih ,  Ting-Chu Ko

IPC: B24B7/22 ,  B24B37/04 ,  B24B37/08 ,  B24B49/12

Abstract: A method includes bonding a first package component on a composite carrier, and performing a first polishing process on the composite carrier to remove a base carrier of the composite carrier. The first polishing process stops on a first layer of the composite carrier. A second polishing process is performed to remove the first layer of the composite carrier. The second polishing process stops on a second layer of the composite carrier. A third polishing process is performed to remove a plurality of layers in the composite carrier. The plurality of layers include the second layer, and the third polishing process stops on a dielectric layer in the first package component.

公开(公告)号：US20240363496A1

公开(公告)日：2024-10-31

申请号：US18771120

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/02311 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/08146

Abstract: A semiconductor device includes a first passivation layer over a circuit and. conductive pad over the first passivation layer, wherein the conductive pad is electrically connected to the circuit. A second passivation layer is disposed over the conductive pad and the first passivation layer, and has a first opening and a second opening. The first opening exposes an upper surface of a layer that extends underneath the conductive pad, and the second opening exposes the conductive pad. A first insulating layer is disposed over the second passivation layer and filling the first and second openings. A through substrate via extends through the insulating layer, second passivation layer, passivation layer, and substrate. A side of the through substrate via and the second passivation layer have a gap that is filled with the first insulating layer. A conductive via extends through the first insulating layer and connecting to the conductive pad.

公开(公告)号：US20240355782A1

公开(公告)日：2024-10-24

申请号：US18756525

申请日：2024-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Tzuan-Horng Liu ,  Chao-Wen Shih ,  Sung-Feng Yeh ,  Nien-Fang Wu

IPC: H01L25/065 ,  H01L21/3105 ,  H01L21/56 ,  H01L21/66 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/544 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/31053 ,  H01L21/56 ,  H01L21/6836 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/544 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L22/32 ,  H01L24/29 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2224/27616 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/8313 ,  H01L2224/83896 ,  H01L2224/92244 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06586

Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

公开(公告)号：US12125820B2

公开(公告)日：2024-10-22

申请号：US17229283

申请日：2021-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chuan-An Cheng ,  Sung-Feng Yeh ,  Chih-Chia Hu

IPC: H01L23/28 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/0652 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06586

Abstract: A method includes bonding a tier-1 device die to a carrier, forming a first gap-filling region to encapsulate the tier-1 device die, forming a first redistribution structure over and electrically connected to the tier-1 device die, and bonding a tier-2 device die to the tier-1 device die. The tier-2 device die is over the tier-1 device die, and the tier-2 device die extends laterally beyond a corresponding edge of the tier-1 device die. The method further includes forming a second gap-filling region to encapsulate the tier-2 device die, removing the carrier, and forming a through-dielectric via penetrating through the first gap-filling region. The through-dielectric via is overlapped by, and is electrically connected to, the tier-2 device die. A second redistribution structure is formed, wherein the first redistribution structure and the second redistribution structure are on opposing sides of the tier-1 device die.

公开(公告)号：US12074140B2

公开(公告)日：2024-08-27

申请号：US17455767

申请日：2021-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Sung-Feng Yeh ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/485 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/485 ,  H01L24/08 ,  H01L24/89 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06548 ,  H01L2225/06568

Abstract: A package includes a first device die, and a second device die bonded to the first device die through hybrid bonding. The second device die is larger than the first device die. A first isolation region encapsulates the first device die therein. The first device die, the second device die, and the first isolation region form parts of a first package. A third device die is bonded to the first package through hybrid bonding. The third device die is larger than the first package. A second isolation region encapsulates the first package therein. The first package, the third device die, and the second isolation region form parts of a second package.

公开(公告)号：US12057439B2

公开(公告)日：2024-08-06

申请号：US17984379

申请日：2022-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Tzuan-Horng Liu ,  Chao-Wen Shih ,  Sung-Feng Yeh ,  Nien-Fang Wu

IPC: H01L25/065 ,  H01L21/3105 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/544 ,  H01L25/00 ,  H01L21/66

CPC classification number: H01L25/0657 ,  H01L21/31053 ,  H01L21/56 ,  H01L21/6836 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/544 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L22/32 ,  H01L24/29 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2224/27616 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/8313 ,  H01L2224/83896 ,  H01L2224/92244 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06586

Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

公开(公告)号：US11908817B2

公开(公告)日：2024-02-20

申请号：US17113357

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Chih-Chia Hu

IPC: H01L23/00 ,  H01L23/498 ,  H03K19/1776 ,  H01L23/495

CPC classification number: H01L24/06 ,  H01L23/49503 ,  H01L23/49827 ,  H03K19/1776

Abstract: A method includes polishing a semiconductor substrate of a first die to reveal first through-vias that extend into the semiconductor substrate, forming a dielectric layer on the semiconductor substrate, and forming a plurality of bond pads in the dielectric layer. The plurality of bond pads include active bond pads and dummy bond pads. The active bond pads are electrically coupled to the first through-vias. The first die is bonded to a second die, and both of the active bond pads and the dummy bond pads are bonded to corresponding bond pads in the second die.

公开(公告)号：US11899242B2

公开(公告)日：2024-02-13

申请号：US17075014

申请日：2020-10-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen

IPC: G02B6/13 ,  H01L23/00 ,  H01L21/56 ,  H01L23/528 ,  G02B6/124 ,  G02B6/12 ,  H01L23/48

CPC classification number: G02B6/13 ,  G02B6/124 ,  H01L21/56 ,  H01L23/528 ,  H01L24/08 ,  H01L24/32 ,  H01L24/83 ,  G02B2006/12107 ,  H01L23/481 ,  H01L2224/08145 ,  H01L2224/32145 ,  H01L2224/80895 ,  H01L2224/83896

Abstract: A packaged device includes an optical IC having an optical feature therein. An interconnect structure including layers of conductive features embedded within respective layers of dielectric materials overlie the optical feature. The interconnect structure is patterned to remove the interconnect structure from over the optical feature and a dielectric material having optically neutral properties, relative to a desired light wavelength(s) is formed over the optical feature. One or more electronic ICs may be bonded to the optical IC to form an integrated package.

公开(公告)号：US20240047338A1

公开(公告)日：2024-02-08

申请号：US18151261

申请日：2023-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Yun-Han Lee ,  Lee-Chung Lu

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/538 ,  H01L23/42 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/49844 ,  H01L25/0655 ,  H01L23/5383 ,  H01L23/42 ,  H01L21/4857 ,  H01L25/50 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/08225 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: In an embodiment, a device includes: a first integrated circuit die including a first device layer and a first front-side interconnect structure, the first front-side interconnect structure including first interconnects interconnecting first devices of the first device layer; a second integrated circuit die including a second device layer and a second front-side interconnect structure, the second front-side interconnect structure including second interconnects interconnecting second devices of the second device layer; and an interposer bonded to a back-side of the first integrated circuit die and to a back-side of the second integrated circuit die, the interposer including a die-to-die interconnect structure, the die-to-die interconnect structure including a pillar, the first integrated circuit die overlapping the pillar.

公开(公告)号：US11894309B2

公开(公告)日：2024-02-06

申请号：US17121140

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Tzuan-Horng Liu ,  Ming-Fa Chen ,  Chao-Wen Shih ,  Sung-Feng Yeh

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L21/66 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4871 ,  H01L21/565 ,  H01L21/78 ,  H01L22/12 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/19103

Abstract: A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies.