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151.发明公开公开(公告)号：US20240365557A1
公开(公告)日：2024-10-31
申请号：US18770406
申请日：2024-07-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Sai-Hooi Yeong , Bo-Feng Young , Yu-Ming Lin , Chi On Chui
CPC classification number: H10B51/20 , H01L29/40111 , H01L29/78391 , H01L29/785 , H01L29/78696 , H10B51/00 , H10B51/10 , H10B51/30
Abstract: A device includes a first channel; a second channel above the first channel; and a gate structure surrounding the first and second channels, wherein the gate structure includes a ferroelectric (FE) layer surrounding the first and second channels and a gate metal layer surrounding the FE layer. The device further includes two first electrodes connected to two sides of the first channel; two second electrodes connected to two sides of the second channel; a dielectric layer between the first and the second electrodes; and an inner spacer layer between the two first electrodes and the gate structure.
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公开(公告)号：US20240334718A1
公开(公告)日：2024-10-03
申请号：US18742427
申请日：2024-06-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chao-I Wu , Yu-Ming Lin
CPC classification number: H10B99/00 , H10B41/20 , H10B43/20 , H10B51/20 , H10B63/00 , H10B63/845 , H10N79/00
Abstract: A memory array includes hybrid memory cells, wherein each hybrid memory cell includes a transistor-type memory including a memory film extending on a gate electrode; a channel layer extending on the memory film; a first source/drain electrode extending on the channel layer; and a second source/drain electrode extending along the channel layer; and a resistive-type memory including a resistive memory layer, wherein the resistive memory layer extends between the second source/drain electrode and the channel layer.
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公开(公告)号：US20240331754A1
公开(公告)日：2024-10-03
申请号：US18742089
申请日：2024-06-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Bo-Feng Young , Sai-Hooi Yeong , Chao-I Wu , Sheng-Chen Wang , Yu-Ming Lin
CPC classification number: G11C11/2257 , G11C11/223 , G11C11/2255 , H10B43/27 , H10B51/10 , H10B51/20 , H10B51/30
Abstract: 3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.
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公开(公告)号：US12101939B2
公开(公告)日：2024-09-24
申请号：US17883834
申请日：2022-08-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Chieh Lu , Sai-Hooi Yeong , Bo-Feng Young , Yu-Ming Lin , Chi On Chui , Han-Jong Chia , Chenchen Jacob Wang
Abstract: A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.
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公开(公告)号：US12069864B2
公开(公告)日：2024-08-20
申请号：US17186852
申请日：2021-02-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Ming Lin , Bo-Feng Young , Sai-Hooi Yeong , Han-Jong Chia , Chi On Chui
Abstract: A device includes a semiconductor substrate; a first word line over the semiconductor substrate, the first word line providing a first gate electrode for a first transistor; and a second word line over the first word line. The second word line is insulated from the first word line by a first dielectric material, and the second word line providing a second gate electrode for a second transistor over the first transistor. The device further including a source line intersecting the first word line and the second word line; a bit line intersecting the first word line and the second word line; a memory film between the first word line and the source line; and a first semiconductor material between the memory film and the source line.
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Patent Agency Ranking
公开(公告)号：US12057344B2
公开(公告)日：2024-08-06
申请号：US17830994
申请日：2022-06-02
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Jia-Chuan You , Chia-Hao Chang , Wai-Yi Lien , Yu-Ming Lin
IPC: H01L21/768 , H01L21/28 , H01L21/8234 , H01L23/485 , H01L29/417 , H01L29/78
CPC classification number: H01L21/76802 , H01L21/28247 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76897 , H01L21/823431 , H01L21/823475 , H01L23/485 , H01L29/41791 , H01L29/785 , H01L21/823425 , H01L2029/7858
Abstract: A method includes forming a gate stack over a substrate and a gate spacer on a sidewall of the gate stack; forming a source/drain region in the substrate and adjacent to the gate spacer; forming a first interlayer dielectric layer over the source/drain region; forming a protective layer over the gate stack and in contact with a top surface of the gate spacer; removing the first interlayer dielectric layer after forming the protective layer; forming an etch stop layer over the protective layer; forming a second interlayer dielectric layer over the etch stop layer; etching the second interlayer dielectric layer and the etch stop layer to form an opening that exposes a top surface of the protective layer; and forming a contact plug in the opening.
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公开(公告)号：US12051750B2
公开(公告)日：2024-07-30
申请号：US17884285
申请日：2022-08-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Chieh Lu , Sai-Hooi Yeong , Bo-Feng Young , Yu-Ming Lin , Chih-Yu Chang
IPC: H01L29/78 , G11C11/22 , H01L29/04 , H01L29/24 , H01L29/66 , H01L29/786 , H10B51/10 , H10B51/20 , H10B51/30
CPC classification number: H01L29/78391 , G11C11/223 , G11C11/2255 , G11C11/2257 , H01L29/04 , H01L29/24 , H01L29/66969 , H01L29/7869 , H10B51/10 , H10B51/20 , H10B51/30
Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor comprising: a ferroelectric (FE) material contacting a word line, the FE material being a hafnium-comprising compound, and the hafnium-comprising compound comprising a rare earth metal; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line.
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公开(公告)号：US12040006B2
公开(公告)日：2024-07-16
申请号：US17815032
申请日：2022-07-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Bo-Feng Young , Sai-Hooi Yeong , Chao-I Wu , Sheng-Chen Wang , Yu-Ming Lin
CPC classification number: G11C11/2257 , G11C11/223 , G11C11/2255 , H10B43/27 , H10B51/10 , H10B51/20 , H10B51/30
Abstract: 3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.
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公开(公告)号：US20240194730A1
公开(公告)日：2024-06-13
申请号：US18585211
申请日：2024-02-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Hsiung Tsai , Shahaji B. More , Yu-Ming Lin , Clement Hsingjen Wann
IPC: H10B12/00 , H01L23/00 , H01L23/522 , H01L23/528 , H01L27/146 , H01L29/94
CPC classification number: H01L28/60 , H01L23/5226 , H01L23/528 , H01L24/18 , H01L24/25 , H01L27/14636 , H01L29/945 , H10B12/038 , H10B12/37 , H01L2224/821
Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) having a portion within the substrate, and an interconnect structure over the DTC and the substrate. The interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the DTC, and a first conductive line electrically coupling the seal ring structure to the first conductive via.
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公开(公告)号：US11910616B2
公开(公告)日：2024-02-20
申请号：US17818562
申请日：2022-08-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Meng-Han Lin , Han-Jong Chia , Sheng-Chen Wang , Feng-Cheng Yang , Yu-Ming Lin , Chung-Te Lin
IPC: H10B51/20 , H01L29/417 , H01L23/535 , H10B51/00 , H10B51/10 , H10B51/30
CPC classification number: H10B51/20 , H01L23/535 , H01L29/41741 , H01L29/41775 , H10B51/00 , H10B51/10 , H10B51/30
Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.
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