公开(公告)号：US07884346B2

公开(公告)日：2011-02-08

申请号：US12295500

申请日：2007-03-27

申请人： Takumi Mikawa ,  Takeshi Takagi

发明人： Takumi Mikawa ,  Takeshi Takagi

IPC分类号： H01L47/00 ,  G11C11/00

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/124 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1691

摘要： A nonvolatile memory element comprising: a first electrode 2; a second electrode 6 formed above the first electrode 2; a variable resistance film 4 formed between the first electrode 2 and the second electrode 6, a resistance value of the variable resistance film 4 being increased or decreased by an electric pulse applied between the first and second electrodes 2, 6; and an interlayer dielectric film 3 provided between the first and second electrodes 2, 6, wherein the interlayer dielectric film 3 is provided with an opening extending from a surface thereof to the first electrode 2; the variable resistance film 4 is formed at an inner wall face of the opening; and an interior region of the opening which is defined by the variable resistance film 4 is filled with an embedded insulating film 5.

摘要翻译： 一种非易失性存储元件，包括：第一电极2; 形成在第一电极2上方的第二电极6; 形成在第一电极2和第二电极6之间的可变电阻膜4，通过施加在第一和第二电极2,6之间的电脉冲，可变电阻膜4的电阻值增加或减小; 以及设置在第一和第二电极2,6之间的层间绝缘膜3，其中层间绝缘膜3设置有从其表面延伸到第一电极2的开口; 可变电阻膜4形成在开口的内壁面上; 并且由可变电阻膜4限定的开口的内部区域填充有嵌入绝缘膜5。

公开(公告)号：US20100271860A1

公开(公告)日：2010-10-28

申请号：US12745300

申请日：2009-09-30

申请人： Shunsaku Muraoka ,  Takeshi Takagi ,  Satoru Mitani ,  Koji Katayama

发明人： Shunsaku Muraoka ,  Takeshi Takagi ,  Satoru Mitani ,  Koji Katayama

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/0033 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/34

摘要： A method of driving a variable resistance element includes: a writing step performed by applying a writing voltage pulse having a first polarity to a variable resistance layer to change a resistance state of the layer from high to low; and an erasing step performed by applying an erasing voltage pulse having a second polarity to the layer to change the state from low to high. Here, |Vw1|>|Vw2| where Vw1 represents a voltage value of the writing voltage pulse for first to N-th writing steps (N≧1) and Vw2 represents a voltage value of the writing voltage pulse for (N+1)-th and subsequent writing steps, and |Ve1|>|Ve2| where Ve1 represents a voltage value of the erasing voltage pulse for first to M-th erasing steps (M≧1) and Ve2 represents a voltage value of the erasing voltage pulse for (M+1)-th and subsequent erasing steps. The (N+1)-th writing step follows the M-th erasing step.

摘要翻译： 驱动可变电阻元件的方法包括：通过将具有第一极性的写入电压脉冲施加到可变电阻层而将层的电阻状态从高变为低的步骤来执行写入步骤; 以及通过将具有第二极性的擦除电压脉冲施加到该层以将状态从低变为高而执行的擦除步骤。 这里，| Vw1 |> | Vw2 | 其中Vw1表示第一至第N写入步骤（N≥1）的写入电压脉冲的电压值，Vw2表示第（N + 1）个和后续写入步骤中的写入电压脉冲的电压值， Ve1 |> | Ve2 | 其中Ve1表示第一至第M擦除步骤（M≥1）的擦除电压脉冲的电压值，Ve2表示（M + 1）次和随后的擦除步骤中的擦除电压脉冲的电压值。 第（N + 1）个写入步骤在第M擦除步骤之后。

公开(公告)号：US20100259966A1

公开(公告)日：2010-10-14

申请号：US12671162

申请日：2009-05-18

申请人： Yoshihiko Kanzawa ,  Satoru Mitani ,  Zhiqiang Wei ,  Takeshi Takagi

发明人： Yoshihiko Kanzawa ,  Satoru Mitani ,  Zhiqiang Wei ,  Takeshi Takagi

IPC分类号： G11C11/00 ,  H01L45/00

CPC分类号： H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/52 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2418 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

摘要： A nonvolatile memory element comprises a first electrode (103), a second electrode (105), and a resistance variable layer (104) which is provided between the first electrode and the second electrode, and is configured to reversibly switch an interelectrode resistance value which is a resistance value between the first electrode and the second electrode, in response to an interelectrode voltage which is an electric potential of the second electrode on the basis of the first electrode, the resistance variable layer includes an oxygen-deficient transition metal oxide, the first electrode side and the second electrode side have an asymmetric structure, a portion of the resistance variable layer which is located at the first electrode side and a portion of the resistance variable layer which is located at the second electrode side are each configured to be selectively placed into one of a low-resistance state and a high-resistance state, so as to attain a stable state in three or more different interelectrode resistance values, the stable state being a state in which the interelectrode resistance value is invariable regardless of a change in the interelectrode voltage within a specified range.

摘要翻译： 非易失性存储元件包括设置在第一电极和第二电极之间的第一电极（103），第二电极（105）和电阻变化层（104），并且被配置为可逆地切换电极间电阻值， 是第一电极和第二电极之间的电阻值，响应于基于第一电极的第二电极的电位的电极间电压，电阻变化层包括缺氧过渡金属氧化物， 第一电极侧和第二电极侧具有不对称结构，位于第一电极侧的电阻变化层的一部分和位于第二电极侧的电阻变化层的一部分分别构成为选择性地 放置成低电阻状态和高电阻状态之一，以达到三个或更多个差异的稳定状态 出现电极间电阻值，稳定状态是不管电极间电压在规定范围内的变化如何，电极间电阻值不变的状态。

公开(公告)号：US20100188884A1

公开(公告)日：2010-07-29

申请号：US12667856

申请日：2009-04-13

申请人： Satoru Mitani ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Zhiqiang Wei ,  Takeshi Takagi

发明人： Satoru Mitani ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Zhiqiang Wei ,  Takeshi Takagi

IPC分类号： G11C11/00 ,  H01L45/00

CPC分类号： H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1625

摘要： A nonvolatile memory element comprises a first electrode (503), a second electrode (505), and a resistance variable layer (504) disposed between the first electrode and the second electrode, a resistance value between the first electrode and the second electrode being switchable reversibly in response to positive and negative electric signals applied between the first electrode and the second electrode; wherein the resistance variable layer includes an oxygen-deficient hafnium oxide; wherein the first electrode and the second electrode comprise elements which are different from each other; and wherein a standard electrode potential V1 of an element forming the first electrode, a standard electrode potential V2 of an element forming the second electrode and a standard electrode potential V0 of hafnium satisfy a relationship of V1

摘要翻译： 非易失性存储元件包括第一电极（503），第二电极（505）和设置在第一电极和第二电极之间的电阻变化层（504），第一电极和第二电极之间的电阻值可切换 响应于施加在第一电极和第二电极之间的正和负电信号而可逆地反转; 其中所述电阻变化层包括缺氧氧化铪; 其中所述第一电极和所述第二电极包括彼此不同的元件; 并且其中形成第一电极的元件的标准电极电位V1，形成第二电极的元件的标准电极电位V2和铪的标准电极电位V0满足V1

公开(公告)号：US20100110766A1

公开(公告)日：2010-05-06

申请号：US12524313

申请日：2008-02-22

申请人： Zhiqiang Wei ,  Kazuhiko Shimakawa ,  Takeshi Takagi ,  Yoshikazu Katoh

发明人： Zhiqiang Wei ,  Kazuhiko Shimakawa ,  Takeshi Takagi ,  Yoshikazu Katoh

IPC分类号： G11C11/00 ,  G11C7/10 ,  G11C7/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/1021

摘要： A nonvolatile memory apparatus comprises a memory array (102) including plural first electrode wires (WL) formed to extend in parallel with each other within a first plane; plural second electrode wires (BL) formed to extend in parallel with each other within a second plane parallel to the first plane and to three-dimensionally cross the plural first electrode wires; and nonvolatile memory elements (11) which are respectively provided at three-dimensional cross points between the first electrode wires and the second electrode wires, the elements each having a resistance variable layer whose resistance value changes reversibly in response to a current pulse supplied between an associated first electrode wire and an associated second electrode wire; and a first selecting device (13) for selecting the first electrode wires, and further comprises voltage restricting means (15) provided within or outside the memory array, the voltage restricting means being connected to the first electrode wires, for restricting a voltage applied to the first electrode wires to a predetermined upper limit value or less; wherein plural nonvolatile memory elements of the nonvolatile memory elements are connected to one first electrode wire connecting the first selecting device to the voltage restricting means.

摘要翻译： 非易失性存储装置包括存储器阵列（102），其包括形成为在第一平面内彼此平行延伸的多个第一电极线（WL） 多个第二电极线（BL），其形成为在与第一平面平行的第二平面内彼此平行延伸并且三维地交叉所述多个第一电极线; 和非易失性存储元件（11），其分别设置在第一电极线和第二电极线之间的三维交叉点处，每个元件具有电阻变化层，其电阻值响应于在 相关联的第一电极线和相关联的第二电极线; 以及用于选择所述第一电极线的第一选择装置（13），并且还包括设置在所述存储器阵列内或外的电压限制装置（15），所述电压限制装置连接到所述第一电极线，用于限制施加到 所述第一电极线达到预定的上限值以下; 其中所述非易失性存储元件的多个非易失性存储元件连接到将所述第一选择装置连接到所述电压限制装置的一个第一电极线。

公开(公告)号：US07692178B2

公开(公告)日：2010-04-06

申请号：US12281034

申请日：2007-03-06

申请人： Yoshio Kawashima ,  Takeshi Takagi ,  Takumi Mikawa ,  Zhiqiang Wei

发明人： Yoshio Kawashima ,  Takeshi Takagi ,  Takumi Mikawa ,  Zhiqiang Wei

IPC分类号： H01L45/00

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1658 ,  H01L45/1675

摘要： A lower electrode layer 2, an upper electrode layer 4 formed above the lower electrode layer 2, and a metal oxide thin film layer 3 formed between the lower electrode layer 2 and the upper electrode layer 4 are provided. The metal oxide thin film layer 3 includes a first region 3a whose value of resistance increases or decreases by an electric pulse that is applied between the lower electrode layer 2 and the upper electrode layer 4 and a second region 3b arranged around the first region 3a and having a larger content of oxygen than the first region 3a, wherein the lower and upper electrode layers 2 and 4 and at least a part of the first region 3a are arranged so as to overlap as viewed from the direction of the thickness of the first region 3a.

摘要翻译： 设置下电极层2，形成在下电极层2上的上电极层4和形成在下电极层2和上电极层4之间的金属氧化物薄膜层3。 金属氧化物薄膜层3包括第一区域3a，其第一区域3a的电阻值通过施加在下电极层2和上电极层4之间的电脉冲和围绕第一区域3a布置的第二区域3b而增大或减小，以及 具有比第一区域3a更大的氧含量，其中下电极层2和上电极层4以及第一区域3a的至少一部分从第一区域的厚度方向观察而重叠 3a。

公开(公告)号：US20100061142A1

公开(公告)日：2010-03-11

申请号：US12532552

申请日：2007-11-30

申请人： Koji Arita ,  Takeshi Takagi ,  Takumi Mikawa ,  Yoshio Kawashima ,  Zhiqiang Wei

发明人： Koji Arita ,  Takeshi Takagi ,  Takumi Mikawa ,  Yoshio Kawashima ,  Zhiqiang Wei

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

摘要： Memory elements (3) arranged in matrix in a memory apparatus (21), each includes a resistance variable element (1) which changes an electrical resistance value in response to an applied electrical pulse having a positive polarity or a negative polarity and maintains the changed electrical resistance value, and a current suppressing element (2) for suppressing a current flowing when the electrical pulse is applied to the resistance variable element. The current suppressing element includes a first electrode, a second electrode, and a current suppressing layer provided between the first electrode and the second electrode, and the current suppressing layer comprises SiNx (x: positive actual number).

摘要翻译： 在存储装置（21）中排列成矩阵的存储元件（3），每个包括电阻变化元件（1），其响应于所施加的具有正极性或负极性的电脉冲改变电阻值，并保持改变 电阻值和电流抑制元件（2），用于抑制当电脉冲施加到电阻可变元件时流动的电流。 电流抑制元件包括第一电极，第二电极和设置在第一电极和第二电极之间的电流抑制层，并且电流抑制层包括SiNx（x：正实数）。

公开(公告)号：US20100032641A1

公开(公告)日：2010-02-11

申请号：US12515379

申请日：2007-11-13

申请人： Takumi Mikawa ,  Takeshi Takagi

发明人： Takumi Mikawa ,  Takeshi Takagi

IPC分类号： H01L45/00 ,  H01L21/28

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/115 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1683

摘要： A nonvolatile semiconductor memory apparatus (10) of the present invention comprises a substrate (10), lower-layer electrode wires (15) provided on the substrate (11), an interlayer insulating layer (16) which is disposed on the substrate (11) including the lower-layer electrode wires (15) and is provided with contact holes at locations respectively opposite to the lower-layer electrode wires (15), resistance variable layers (18) which are respectively connected to the lower-layer electrode wires (15); and non-ohmic devices (20) which are respectively provided on the resistance variable layers (18) such that the non-ohmic devices are respectively connected to the resistance variable layers (18). The non-ohmic devices (20) each has a laminated-layer structure including plural semiconductor layers, a laminated-layer structure including a metal electrode layer and an insulator layer, or a laminated-layer structure including a metal electrode layer and a semiconductor layer. One layer of the laminated-layer structure is embedded to fill each of the contact holes and the semiconductor layer or the insulator layer which is the other layer of the laminated-layer structure has a larger area than an opening of each of the contact holes and is provided on the interlayer insulating layer (16).

摘要翻译： 本发明的非易失性半导体存储装置（10）具备基板（10），设置在基板（11）上的下层电极布线（15），设置在基板（11）上的层间绝缘层（16） ），并且在分别与下层电极线（15）相对的位置设置接触孔，电阻变化层（18）分别与下层电极线（15）连接 15）; 和非欧姆器件（20），其分别设置在电阻变化层（18）上，使得非欧姆器件分别连接到电阻变化层（18）。 非欧姆装置（20）各自具有包括多个半导体层的层叠层结构，包括金属电极层和绝缘体层的层叠层结构，或者包括金属电极层和半导体层的层叠层结构 。 嵌入层叠层结构的一层以填充每个接触孔，作为层叠层结构的另一层的半导体层或绝缘体层的面积比每个接触孔的开口大， 设置在层间绝缘层（16）上。

公开(公告)号：US20090273784A1

公开(公告)日：2009-11-05

申请号：US11987714

申请日：2007-12-04

申请人： Mieko Yamagaki ,  Yu Mimura ,  Kazuyou Mizuno ,  Takeshi Takagi

发明人： Mieko Yamagaki ,  Yu Mimura ,  Kazuyou Mizuno ,  Takeshi Takagi

IPC分类号： G01J4/00

CPC分类号： G01J4/00

摘要： The invention provides a Stokes parameter measurement device and Stokes parameter measurement method that enable high-precision measurement. The Stokes parameter measurement device comprises a polarization splitting device which comprises an optical element formed of a birefringent crystal material and which, by means of the optical element, splits signal light to be measured into a plurality of polarized light beams and adjusts the polarization state of one or more among the plurality of polarized light beams, and a light-receiving portion for performing photoelectric conversion of an optical component of the signal light split by and emitted from the polarization splitting device.

摘要翻译： 本发明提供了能够进行高精度测量的斯托克斯参数测量装置和斯托克斯参数测量方法。 斯托克斯参数测量装置包括偏振分离装置，其包括由双折射晶体材料形成的光学元件，并且通过光学元件将待测量的信号光分解为多个偏振光束并调节偏振态 多个偏振光束中的一个或多个，以及用于对由偏振分离装置分离和发射的信号光的光学分量执行光电转换的光接收部分。

公开(公告)号：US07554139B2

公开(公告)日：2009-06-30

申请号：US11568404

申请日：2005-04-11

申请人： Akira Inoue ,  Haruyuki Sorada ,  Yoshio Kawashima ,  Takeshi Takagi

发明人： Akira Inoue ,  Haruyuki Sorada ,  Yoshio Kawashima ,  Takeshi Takagi

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/76229 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/088

摘要： A production method for a semiconductor device according to the present invention includes: step (A) of providing a substrate including a semiconductor layer having a principal face, the substrate having a device isolation structure (STI) formed in an isolation region 70 for partitioning the principal face into a plurality of device active regions 50, 60; step (B) of growing an epitaxial layer containing Si and Ge on selected device active regions 50 among the plurality of device active regions 50, 60 of the principal face of the semiconductor layer; and step (C) of forming a transistor in, among the plurality of device active regions 50, 60, each of the device active regions 50 on which the epitaxial layer is formed and each of the device active regions A2 on which the epitaxial layer is not formed. Step (A) includes step (a1) of forming, in the isolation region 70, a plurality of dummy regions 80 surrounded by the device isolation structure (STI), and step (B) includes step (b1) of growing a layer of the same material as that of the epitaxial layer on selected regions among the plurality of dummy regions 80.

摘要翻译： 根据本发明的半导体器件的制造方法包括：步骤（A），其提供包括具有主面的半导体层的衬底，所述衬底具有形成在隔离区域70中的器件隔离结构（STI），用于分割 主面进入多个设备有源区域50,60; 在半导体层的主面的多个器件有源区50,60中的选定器件有源区50上生长含有Si和Ge的外延层的工序（B） 以及在多个器件有源区域50,60之间形成晶体管的步骤（C），在其上形成有外延层的器件有源区域50中的每一个，外延层上的每个器件有源区域A2 没有形成。 步骤（A）包括在隔离区域70中形成被器件隔离结构（STI）包围的多个虚拟区域80的步骤（a1），步骤（B）包括步骤（b1） 与多个虚拟区域80中的选定区域上的外延层相同的材料。