公开(公告)号：US4980576A

公开(公告)日：1990-12-25

申请号：US364172

申请日：1989-06-12

Applicant: Domenico Rossi ,  Claudio Diazzi

Inventor： Domenico Rossi ,  Claudio Diazzi

IPC: H02M3/07 ,  H02M3/155 ,  H02M3/156 ,  H02M7/538 ,  H03K17/06 ,  H03K17/082 ,  H03K17/60

CPC classification number: H03K17/0826 ,  H02M3/156 ,  H02M7/538 ,  H03K17/063

Abstract: The circuit comprises a tank capacitance and a charge circuit supplied with the same voltage as the bridge and comprising an inductance and a control transistor. There is also provided a control circuit, which comprises an oscillator controlling the periodic switching of control transistor and a comparator which controls the momentary clamping of control transistor in the condition wherein the charge circuit is interrupted when the difference between the voltage across capacitance and the power supply voltage exceeds a preset maximum value and the unclamping of the same transistor when such difference falls below a preset minimum value. A further comparator similarly clamps control transistor if there is an excess current in the transistor itself.

公开(公告)号：US4965215A

公开(公告)日：1990-10-23

申请号：US287067

申请日：1988-12-21

Applicant: Raffaele Zambrano ,  Salvatore Musumeci

Inventor： Raffaele Zambrano ,  Salvatore Musumeci

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/761 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H01L29/732

CPC classification number: H01L21/8222 ,  H01L21/761

Abstract: The device uses the horizontal insulating region and the buried layer as the power transistor base and emitter respectively. An epitaxial growth is interposed between the two diffusions needed to form the aforesaid regions and those needed to create the base and the emitter of the transistor of the integrated control circuit.

公开(公告)号：US4957881A

公开(公告)日：1990-09-18

申请号：US424450

申请日：1989-10-20

Applicant: Pier L. Crotti

Inventor： Pier L. Crotti

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/76885 ,  Y10S438/978

Abstract: A process for forming self-aligned metal-semiconductor contacts in a device comprising MISFET type structures essentially comprises conformably depositing a matrix metallic layer on the front of the wafer and the subsequent deposition of a planarization SOG layer. After having used a noncritical mask for defining the "length" of the selfaligned contacts to be formed, the SOG layer is etched until leaving a residue layer on the bottom of the valleys of the conformably deposited matrix metallic layer in areas between two adjacent gate lines of polysilicon. A selective etching of the matrix layer using said SOG residues as a mask, defines the contacts, self-aligned in respect to the opposite spacers of two adjacent polysilicon gate lines. An insulating dielectric layer is deposited and etched until exposing the peaks of the preformed contacts. Over such an advantageously planarized surface contacts on the polysilicon gate lines may be defined by a customary masking process and finally the second level metal is deposited.

公开(公告)号：US4947237A

公开(公告)日：1990-08-07

申请号：US106016

申请日：1987-10-01

Applicant: Marzio Fusaroli

Inventor： Marzio Fusaroli

IPC: H01L23/50 ,  H01L23/495

CPC classification number: H01L23/49568 ,  H01L2924/0002

Abstract: An integrated circuit package is described that provides increased heat dissipation of heat generated in an integrated circuit chip that can be positioned within the package. This increased heat dissipation characteristic is achieved by configuring enlarged metal areas of the lead frame of the package that are extensions of the flag area. The flag area is the portion of the lead frame to which the integrated circuit chip is mounted in the assembly of the semiconductor package. The increased lead frame area provides increased contact with the package housing and provides a thermal conduction path in close proximity to the exterior surface of the package housing. The integrated circuit chip has a more efficient thermal path to the ambient air thermal heat sink.

Abstract translation: 描述了一种集成电路封装，其提供在可以位于封装内的集成电路芯片中产生的热量的增加的散热。 通过配置作为标志区域的延伸的包装的引线框架的扩大的金属区域来实现增加的散热特性。 标志区域是集成电路芯片安装在半导体封装的组件中的引线框架的部分。 增加的引线框架区域提供与封装壳体的增加的接触并且提供紧邻封装壳体的外表面的热传导路径。 集成电路芯片具有对环境空气热散热器更有效的热路径。

公开(公告)号：US4931676A

公开(公告)日：1990-06-05

申请号：US298652

申请日：1989-01-18

Applicant: Antonella Baiocchi ,  Angelo Alzati

Inventor： Antonella Baiocchi ,  Angelo Alzati

IPC: H03K17/0412 ,  H03K17/687 ,  H03K17/695

CPC classification number: H03K17/6871 ,  H03K17/04123

Abstract: A low-absorption circuit device for controlling into the on state a power transistor, in particular a D MOS transistor having conventional gate, drain, and source electrodes, and adapted to drive electrical loads by changing over from an off state to an on state in which there appears on the gate electrode a predetermined voltage value, comprises a first turn-on circuit connected to one pole of a voltage supply, a second turn-on circuit connected to another supply voltage pole, and a comparator having respective inputs connected to the gate electrode of the power transistor and to a reference voltage pole as well as respective outputs connected to each respective turn-on circuit to activate said circuits alternately based on a comparison of the gate voltage of the power transistor with the predetermined reference voltage.

公开(公告)号：US4920077A

公开(公告)日：1990-04-24

申请号：US249788

申请日：1988-09-27

Applicant: Marco Mora

Inventor： Marco Mora

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/316 ,  H01L21/324 ,  H01L21/8238

CPC classification number: H01L21/324 ,  H01L21/02129 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31612 ,  Y10S438/909

Abstract: A method is disclosed wherein monolythic integrated circuit undergo a so-called aluminum annealing process step and so-called passivation step carried out within a deposition reactor of the PECVD type at a temperature of 420.degree. to 450.degree. C. and a pressure of 1 to 1.5 Torr. Applications of this method results in an increased electrical yield of the circuits produced and a reduction of their manufacturing costs.

公开(公告)号：US4918399A

公开(公告)日：1990-04-17

申请号：US281725

申请日：1988-12-09

Applicant: Daniele Devecchi ,  Guido Torelli

Inventor： Daniele Devecchi ,  Guido Torelli

IPC: H03F3/45

CPC classification number: H03F3/45941 ,  H03F3/45475 ,  H03F2203/45424

Abstract: In a chain of fully differential amplifiers, having at least two cascaded amplifiers, the stabilization of the output common mode voltage of an amplifier is implemented by sensing the value of such a voltage by means of a dedicated terminal connected to a circuit node corresponding to the connected in common sources of the input differential pair of transistors of an amplifier which follows in the chain of cascaded amplifiers. Such a voltage is compared with a reference voltage to which, by means of a level shifting circuit, a voltage equivalent to the threshold voltage of the transistors forming the input pair is subtracted thus obtaining an error signal of the output common voltage of the amplifier to be stabilized which may be applied to a dedicated control terminal thereof. The system of the invention provides for the sensing of the output common mode voltage without loading the outputs of the amplifier to be stabilized and it is more easily implemented than known systems.

公开(公告)号：US4916408A

公开(公告)日：1990-04-10

申请号：US277078

申请日：1988-11-28

Applicant: Fabrizio Stefani ,  Alberto Gola ,  Gianluigi Pessina

Inventor： Fabrizio Stefani ,  Alberto Gola ,  Gianluigi Pessina

IPC: H03F1/34 ,  H03F1/02 ,  H03F3/20 ,  H03F3/21 ,  H03F3/213 ,  H03F3/30

CPC classification number: H03F1/0261 ,  H03F3/211

Abstract: An improved power stage with increased output dynamics. The stage comprises a power amplifier having a first inverting input, a second non-inverting input, an output to be connected to a load and a feedback network comprising a first resistor connected between the inverting input and the output of the power amplifier and a second resistor connected between the first inverting input and a first line set to a first reference voltage by means of a voltage generator with preset values. The stage furthermore comprises an input voltage generator generating an input voltage signal to be amplified and connected between the second non-inverting input and a second line set to a second reference voltage different from said first reference voltage. In order to increase the output dynamics, in particular in the case of low power supply voltage, said voltage generator arranged between the second resistor and said input voltage generator, and generating a voltage which is variable in inverse proportion to the input voltage signal, with respect to the second reference voltage.

公开(公告)号：US4904959A

公开(公告)日：1990-02-27

申请号：US310175

申请日：1989-02-13

Applicant: Silvano Gornati

Inventor： Silvano Gornati

IPC: H03K4/50 ,  H03K3/0231 ,  H03K4/502

CPC classification number: H03K4/502 ,  H03K3/0231

Abstract: This high-precision oscillator stage, with reduced response times, includes only NPN transistors on the signal path and comprises a threshold detector circuit connected to a first and to a second threshold voltage and to the output of the stage so as to generate a differential voltage output signal which switches when each voltage threshold is reached, a control and memory circuit comprising a differential voltage detector connected to the output of the threshold detector and generating a charge and discharge signal depending on the state of the circuit, a memory element controlled by the differential voltage detector to maintain the charge and discharge states and an output driving circuit connected to the control and memory circuit so as to supply an external capacitor with constant currents so as to alternately and periodically charge and discharge the capacitor.

公开(公告)号：US4879641A

公开(公告)日：1989-11-07

申请号：US263935

申请日：1988-10-28

Applicant: Domenico Rossi ,  Andrea Cuomo

Inventor： Domenico Rossi ,  Andrea Cuomo

IPC: H02M7/5387 ,  H02P7/00

CPC classification number: H02M7/53871 ,  H02P7/04 ,  H02M2003/1555

Abstract: A circuit for sensing the magnitude and sense of a current flowing through the load of an H-bridge stage driving the load in a switching mode by means of a clocked, square-wave driving signal and the inverted signal thereof applied, respectively, to two pairs of analog switches arranged in a bridge configuration and functionally switching the load between a supply node and a virtual ground node is made by utilizing a single sensing resistance connected between the virtual ground node and the real ground node of the circuit, the signal across the resistance and the inverted signal thereof are fed to two inputs of an analog multiplex whose output signal is fed to the input of a comparator in order to obtain at the output of the latter a signal with an amplitude proportional to the intensity of the current and a polarity determined by the polarity of a reference voltage which is applied to another input of the comparator. The PWM control loop may then be completed by means of a flip-flop to the inputs of which the output signal of the comparator and a clock signal are applicable in order to generate at the output of the flip-flop the clocked driving signal.

Abstract translation: 一种电路，用于感测流过H桥级的负载的电流的大小和感测，该H电桥级通过时钟方波驱动信号及其反相信号分别以切换模式驱动负载，分别施加到两个 通过利用连接在电路的虚拟接地节点和实际接地节点之间的单个感测电阻来实现布置成桥式配置并且功能地切换供电节点和虚拟接地节点之间的负载的模拟开关对， 电阻及其反相信号被馈送到模拟多路复用的两个输入，其输出信号被馈送到比较器的输入端，以便在其输出端获得具有与电流的强度成正比的信号和 极性由施加到比较器的另一个输入的参考电压的极性决定。 然后可以通过触发器将PWM控制环路完成到其比较器的输出信号和时钟信号的输入端，以在触发器的输出端产生时钟驱动信号。