公开(公告)号：US07642876B2

公开(公告)日：2010-01-05

申请号：US11261449

申请日：2005-10-28

Applicant: Nitin Agarwal

Inventor： Nitin Agarwal

IPC: H03K7/08 ,  H03K9/08

CPC classification number: H03K7/08

Abstract: A PWM generator system provides improved duty cycle resolution using a sub-cycle generator for generating a sub-cycle with a period that is a small fraction of the maximum PWM period to be generated. An integral sub-cycle estimator is coupled to said sub-cycle generator for determining the integral number of said sub-cycles for on and off time of the PWM waveform. An additional sub-cycle estimator determines the additional fractional sub-cycle required to provide the on and off time. A timer coupled to the integral sub cycle estimator and the additional sub cycle estimator controls PWM output switching for the on and off time of the integral and additional fractional sub cycles.

Abstract translation: PWM发生器系统使用子周期发生器提供改进的占空比分辨率，用于产生具有要产生的最大PWM周期的一小部分的周期的子周期。 积分子周期估计器耦合到所述子周期发生器，以确定用于PWM波形的导通和截止时间的所述子周期的整数。 附加的子周期估计器确定提供开启和关闭时间所需的附加分数子周期。 耦合到积分子周期估计器和附加子周期估计器的定时器控制用于积分和附加分数子周期的开和关时间的PWM输出切换。

公开(公告)号：US07529862B2

公开(公告)日：2009-05-05

申请号：US11512750

申请日：2006-08-30

Applicant: Soniya T. Isani ,  Hariharasudhan Kalayamputhur Radhakrishnan

Inventor： Soniya T. Isani ,  Hariharasudhan Kalayamputhur Radhakrishnan

IPC: G06F3/00

CPC classification number: G06F13/4291 ,  G06F13/28 ,  G06F2213/0016

Abstract: An area efficient system that includes a first circuit to synchronize a clock signal and a data signal and a data retaining and processing device to receive data from said data bus to thereby generate a status signal indicating the receipt of data by said area efficient system; a reference bus address and said data bus. The system also includes a device to compare the reference bus address with the content of memory for generating an address matching signal and a control signal generator to govern the data write signal generation for said shifting means. The system further includes a sequencer to read and write data from/to said data retaining and processing device in a plurality of subcycles for efficiently accessing storage buffers and a direct storage access controlling means for generating interrupt signals and access request signals.

Abstract translation: 一种区域有效的系统，其包括使时钟信号和数据信号同步的第一电路和数据保持和处理装置，以从所述数据总线接收数据，从而生成指示由所述区域有效系统接收数据的状态信号; 参考总线地址和所述数据总线。 该系统还包括用于将参考总线地址与用于产生地址匹配信号的存储器的内容进行比较的装置和用于控制所述移位装置的数据写入信号生成的控制信号发生器。 该系统还包括一个定序器，用于从多个子周期中的数据保存和处理设备读取和写入用于有效访问存储缓冲器的数据和用于产生中断信号和访问请求信号的直接存储访问控制装置。

公开(公告)号：US07522439B2

公开(公告)日：2009-04-21

申请号：US11321749

申请日：2005-12-29

Applicant: Anoop Khurana ,  Rajiv Kumar

Inventor： Anoop Khurana ,  Rajiv Kumar

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A low power content addressable memory system comprising an array of content addressable memory cells organized as a plurality of equal sized CAM cell groups, each CAM cell group having one or more CAM cells; a valid entry tag bit associated with each said content addressable memory cell; a match output generator connected to the output of each CAM cell and an enabling means having its first input connected to the valid entry tag bit, its second input connected to a match control signal and its output connected to the corresponding match output generator such that said match output generator is enabled only if said valid entry tag bit indicates a valid entry.

Abstract translation: 一种低功率内容可寻址存储器系统，包括被组织为多个相等大小的CAM单元组的内容可寻址存储器单元的阵列，每个CAM单元组具有一个或多个CAM单元; 与每个所述内容可寻址存储器单元相关联的有效输入标签位; 连接到每个CAM单元的输出的匹配输出发生器和启用装置，其第一输入连接到有效输入标签位，其第二输入连接到匹配控制信号，其输出连接到相应的匹配输出发生器，使得所述 匹配输出生成器只有在所述有效条目标签位指示有效条目时被使能。

公开(公告)号：US20090091358A1

公开(公告)日：2009-04-09

申请号：US12006091

申请日：2007-12-28

Applicant: Vijender Singh Chauhan ,  Kallol Chatterjee ,  Paras Garg

Inventor： Vijender Singh Chauhan ,  Kallol Chatterjee ,  Paras Garg

IPC: H03B1/00

CPC classification number: H03K19/00384 ,  H03K19/018521

Abstract: The present invention provides a compensated output buffer circuit providing an improved slew rate control and a method for minimizing the variations in the current slew rate of the buffer over process, voltage and temperature (PVT) conditions. The output buffer circuit includes a split-gate compensated driver and a slew rate control circuit. Accordingly, a desired slew rate can be maintained with fewer variations over wide range of variations in PVT conditions. The slew rate control circuit consists of two separate slew rate control circuits called a pull-up PMOS driver and a pull-down NMOS driver. To minimize the variations in the slew rate, the rising and falling time of the pre-driver nodes are controlled by means of two current control networks, which are compensated against PVT variations by using separate NMOS and PMOS digital compensation codes. The compensation codes are provided by a compensation circuit, which sense the variation in PVT conditions and reflect these variations in the compensation codes.

Abstract translation: 本发明提供一种补偿输出缓冲电路，其提供改进的转换速率控制和用于最小化缓冲器在过程，电压和温度（PVT）条件下的电流转换速率的变化的方法。 输出缓冲电路包括分闸门补偿驱动器和转换速率控制电路。 因此，可以在PVT条件的宽泛变化范围内以较少的变化来维持期望的转换速率。 转换速率控制电路由两个单独的转换速率控制电路组成，称为上拉PMOS驱动器和下拉式NMOS驱动器。 为了最小化转换速率的变化，预驱动器节点的上升和下降时间通过两个电流控制网络来控制，这两个电流控制网络通过使用单独的NMOS和PMOS数字补偿代码来补偿PVT变化。 补偿代码由补偿电路提供，该补偿电路检测PVT条件的变化并反映补偿代码中的这些变化。

公开(公告)号：US20090027126A1

公开(公告)日：2009-01-29

申请号：US12178769

申请日：2008-07-24

Applicant: Pratap Narayan Singh ,  Chandrajit Debnath

Inventor： Pratap Narayan Singh ,  Chandrajit Debnath

IPC: H03F3/45

CPC classification number: H03F3/45188 ,  H03F2200/453 ,  H03F2203/45292 ,  H03F2203/45356 ,  H03F2203/45626 ,  H03F2203/45682

Abstract: An adaptive biasing technique improves fully differential gain boosted operational amplifiers transient characteristics and reduces power consumption. An adaptive biasing module includes a bias generation module and a bias replication module. The bias generation module generates a first control signal (VCMNB) and the first control signal is applied as an output common mode of a differential booster (inside the bias replication module). The bias replication module is coupled to the bias generation module for equalizing a common mode of the differential booster with the first control signal (VCMNB).

Abstract translation: 自适应偏置技术可以完全提高差分增益提升运算放大器的瞬态特性并降低功耗。 自适应偏置模块包括偏置生成模块和偏置复制模块。 偏置产生模块产生第一控制信号（VCMNB），并且将第一控制信号作为差分增强器的输出共模（偏置复制模块内部）施加。 偏置复制模块耦合到偏置产生模块，用于利用第一控制信号（VCMNB）对差分升压器的共模进行均衡。

公开(公告)号：US07483289B2

公开(公告)日：2009-01-27

申请号：US11195337

申请日：2005-08-02

Applicant: Seema Jain

Inventor： Seema Jain

IPC: G11C11/00

CPC classification number: G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1096 ,  G11C7/22 ,  G11C11/413

Abstract: An improved synchronous SRAM capable of faster read-modify-write cycle time using separate input and output terminals. It describes the circuitry for performing a RMW operation in a memory module at high frequency in a nanometer technology. A byte write enable bus is incorporated into the device so as to provide the flexibility of modification and correction at selective columns, keeping rest of the columns unaltered. The termination of read operation and the triggering of write operation is done by the activation of same signal. Also described is the provision for tuning the circuitry for triggering write operation depending on the time taken by the controller to modify and revise the read-out data.

Abstract translation: 一种改进的同步SRAM，能够使用单独的输入和输出端子更快地读取 - 修改 - 写入周期时间。 它描述了在纳米技术中以高频率在存储器模块中执行RMW操作的电路。 一个字节写使能总线被并入设备，以便提供选择性列修改和修正的灵活性，保持列不变。 读操作的终止和写操作的触发是通过激活相同的信号完成的。 还描述了根据控制器修改和修改读出数据所花费的时间来调整用于触发写入操作的电路的规定。

公开(公告)号：US07475105B2

公开(公告)日：2009-01-06

申请号：US11152954

申请日：2005-06-15

Applicant: Deboleena Minz

Inventor： Deboleena Minz

IPC: G06F7/50

CPC classification number: G06F7/503 ,  G06F7/501

Abstract: A one bit full adder with sum and carry outputs performs independent functions. The full adder includes at least one look up table (LUT) for implementing a sum function, and at least one carry circuit for implementing a carry/borrow function. The carry circuit includes a first multiplexer having first and second inputs, a select line input, and a carry/borrow output. The carry circuit also includes an AND gate, an OR gate and an XOR gate. The AND gate has two inputs, and an output connected to the first input of the first multiplexer. The OR gate has two inputs, and an output connected to the second input of the first multiplexer. The XOR gate has a first input, and an output connected to the select line input of the first multiplexer. A second multiplexer has an output connected to the first input of the XOR gate. The at least one LUT and the at least one carry circuit provides independent sum and carry outputs for different function requirements.

Abstract translation: 具有和和进位输出的一位全加器执行独立功能。 全加器包括用于实现和功能的至少一个查找表（LUT）和用于实现进位/借位功能的至少一个进位电路。 进位电路包括具有第一和第二输入，选择线输入和进位/借位输出的第一多路复用器。 进位电路还包括与门，或门和异或门。 与门有两个输入端，一个输出端连接到第一个多路复用器的第一个输入端。 或门有两个输入端，一个输出端连接到第一个多路复用器的第二个输入端。 异或门具有第一输入端，输出端连接到第一多路复用器的选择线输入端。 第二多路复用器具有连接到异或门的第一输入的输出。 至少一个LUT和至少一个进位电路为不同的功能要求提供独立的和并携带输出。

公开(公告)号：US07460718B2

公开(公告)日：2008-12-02

申请号：US11155391

申请日：2005-06-17

Applicant: Antoine Gautier ,  Mahesh Chandra

Inventor： Antoine Gautier ,  Mahesh Chandra

IPC: G06K9/36

CPC classification number: H04N19/60 ,  H04N19/85 ,  H04N2201/33378

Abstract: The conversion device includes an input for receiving data corresponding to an image to be displayed. The received data is in a JPEG decoder output data format A processor is included for reconstructing and writing the image to be displayed into the image memory, in a display module expected input data format. The bandwidth of the image memory is greater than one byte. The processor is fully hardwired and includes a first logic stage for writing the received data byte by byte into an intermediate memory at chosen addresses such that the written data form a sequence of data in the display module expected input data format, and a second logic stage for reading the written data in the intermediate memory, forming successive packets of read data having a size corresponding to the bandwidth, and successively writing the packets into the image memory at chosen addresses such that the written packets together form all the lines of the image.

Abstract translation: 转换装置包括用于接收与要显示的图像相对应的数据的输入。 接收到的数据是JPEG解码器输出数据格式。 包括处理器，用于以显示模块期望的输入数据格式重建和写入要显示的图像到图像存储器中。 图像存储器的带宽大于一个字节。 处理器是完全硬连线的，并且包括用于逐字地将所接收的数据逐字地写入到所选地址的中间存储器中的第一逻辑级，使得写入的数据形成显示模块预期输入数据格式的数据序列，以及第二逻辑级 用于读取中间存储器中的写入数据，形成具有与带宽相对应的大小的连续的读取数据分组，并且以选定的地址将分组顺序地写入图像存储器，使得所写入的分组一起形成图像的所有行。

公开(公告)号：US07436201B2

公开(公告)日：2008-10-14

申请号：US11618116

申请日：2006-12-29

Applicant: Ashish Kumar

Inventor： Ashish Kumar

IPC: H03K17/16

CPC classification number: H03K19/0016

Abstract: An architecture for reducing leakage component in semiconductor devices using a gated power supply is based on the supply being split into two parts. An alternate inverter is connected to a different power rail derived from the same single power rail. The power rails are enabled and disabled according to the value of a standby signal and an input signal. The standby signal is high in the standby mode and low in the active mode.

Abstract translation: 使用门控电源减少半导体器件的漏电元件的架构是基于电源分为两部分。 另一个逆变器连接到由同一单个电源轨道导出的不同电源轨。 根据待机信号和输入信号的值，启用和禁用电源轨。 待机信号在待机模式为高电平，低电平有效。

公开(公告)号：US07433239B2

公开(公告)日：2008-10-07

申请号：US11323953

申请日：2005-12-30

Applicant: Vivek Nautiyal ,  Ashish Kumar

Inventor： Vivek Nautiyal ,  Ashish Kumar

IPC: G11C16/06

CPC classification number: G11C8/08 ,  G11C11/413

Abstract: The memory includes a plurality of access transistors with each of the access transistors coupled to one of the wordlines at its control terminal and connected to one of the bitlines at its output terminal. A plurality of memory cells have each output coupled to an input terminal of one of the access transistors so that the access transistors share one of the wordlines and are coupled to different bitlines. A wordline driver coupled to each wordline has the ability of generating a variable voltage at its output responsive to the wordline driver control inputs and voltage at its ground supply node. A plurality of grouped voltage supply lines are coupled to a group of the wordline drivers for inducing a variable reference voltage or ground supply at the ground supply node. A voltage switching logic switches the voltage for the variable ground supply responsive to a ground control input.

Abstract translation: 存储器包括多个存取晶体管，其中每个存取晶体管在其控制端耦合到一条字线，并在其输出端连接到一条位线。 多个存储单元具有耦合到一个存取晶体管的输入端的每个输出，使得存取晶体管共享一条字线并耦合到不同的位线。 耦合到每个字线的字线驱动器具有响应于字线驱动器控制输入和其地面电源节点处的电压而在其输出处产生可变电压的能力。 多个组合的电压供应线耦合到一组字线驱动器，用于在接地电源节点处引入可变参考电压或地电源。 电压开关逻辑根据接地控制输入切换可变接地电源的电压。