公开(公告)号：US10236876B2

公开(公告)日：2019-03-19

申请号：US15748156

申请日：2016-05-11

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Chuan Luo

IPC: H03K17/06 ,  H03K17/16 ,  H03K17/687 ,  H03K17/10 ,  H03K19/0175

Abstract: A switch control circuit includes: a clock circuit (110) configured to generate a first clock control signal (CLK1) and a second clock control signal (CLK2); a voltage boosting circuit (120) configured to receive the second clock control signal (CLK2) and an operating voltage outputted by the power source (VDD); and boost the operating voltage by a preset value to form a switch control signal (H1) under the control of the second clock control signal (CLK2); and an inverting circuit (130) configured to receive the first clock control signal (CLK1) and the switch control signal (H1), and determine whether or not to output the switch control signal (H1) to the switch circuit according to the first clock control signal (CLK1), so as to control on/off of the switch circuit.

公开(公告)号：US20190057960A1

公开(公告)日：2019-02-21

申请号：US15770624

申请日：2016-08-19

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD

Inventor： Kui XIAO

IPC: H01L27/02 ,  H01L29/866 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L29/0696 ,  H01L29/16 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/866

Abstract: Disclosed is a semiconductor device having an e1ectrostatic discharge protection structure. The e1ectrostatic discharge protection structure is a diode connected between a gate e1ectrode and a source e1ectrode of the semiconductor device. The diode comprises a diode body and two connection portions connected to two ends of the diode body and respectively used for electrically connecting to the gate e1ectrode and the source e1ectrode. Lower parts of the two connection portions are respective1y provided with a trench. An insulation 1ayer is provided on an inner surface of the trench and the surface of a substrate between trenches. The diode body is provided on the insu1ation 1ayer on the surface of the substrate. The connection portions respectively extend downwards into respective trenches from one end of the diode body. A dielectric layer is provided on the diode, and a meta1 conductor 1ayer is provided on the dielectric layer.

公开(公告)号：US20180342609A1

公开(公告)日：2018-11-29

申请号：US15779666

申请日：2016-08-25

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun QI ,  Guipeng SUN

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/08

Abstract: A lateral diffused metal oxide semiconductor field effect transistor, comprising a substrate, a gate, a source, a drain, a body region, a field oxide region between the source and drain, and a first well region and second well region on the substrate. The second well region below the gate is provided with a plurality of gate doped regions, and a polycrystalline silicon gate of the gate is a multi-segment structure, each segment being separated from the others, with each gate doped region being disposed below the spaces between each segment of the polycrystalline silicon gate. Each of the gate doped regions is electrically connected to the segment that is in a direction nearest the source from among the two polycrystalline silicon gate segments on either side thereof.

公开(公告)号：US20180277532A1

公开(公告)日：2018-09-27

申请号：US15764394

申请日：2016-08-24

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Zheng BIAN

IPC: H01L27/02

CPC classification number: H01L27/0255 ,  H01L27/0629 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/7801 ,  H01L29/866

Abstract: A semiconductor device, having an electro-static discharge (ESD) protection structure, comprises: a diode, connected between a gate and a source of the semiconductor device, and comprising a diode main body, and two connection portions, respectively connected to two terminals of the diode main body and respectively electrically connected to the gate and the source; and a substrate comprising two insulation pads disposed thereon and separated from each other. A surface of the substrate between the insulation pads is provided with an insulation layer. The diode main body is arranged on the insulation layer. The two connection portions are configured to extend, respectively, from either end of the diode main body to the insulation pad on the corresponding side. A dielectric layer is arranged on the diode and the two insulation pads, and a metal conduction line layer is arranged on the dielectric layer.

公开(公告)号：US20180134548A1

公开(公告)日：2018-05-17

申请号：US15573280

申请日：2016-05-10

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Errong JING

IPC: B81C1/00 ,  G01J5/20

CPC classification number: B81C1/00182 ,  B81B7/02 ,  B81C1/00 ,  B81C1/00476 ,  B81C2201/0108 ,  B81C2201/0109 ,  B81C2201/0132 ,  G01J5/20

Abstract: An MEMS double-layer suspension microstructure manufacturing method, comprising: providing a substrate (100); forming a first dielectric layer (200) on the substrate (100); patterning the first dielectric layer (200) to prepare a first film body (210) and a cantilever beam (220) connected to the first film body (210); forming a sacrificial layer (300) on the first dielectric layer (200); patterning the sacrificial layer (300) located on the first film body (210) to make a recess portioned portion (310) for forming a support structure (420), with the first film body (210) being exposed at the bottom of the recess portioned portion (310); forming a second dielectric layer (400) on the sacrificial layer (300); patterning the second dielectric layer (400) to make the second film body (410) and the support structure (420), with the support structure (420) being connected to the first film body (210) and the second film body (410); and removing part of the substrate under the first film body (210) and removing the sacrificial layer (300) to obtain the MEMS double-layer suspension microstructure. In addition, an MEMS infrared detector is also disclosed.

公开(公告)号：US20180122794A1

公开(公告)日：2018-05-03

申请号：US15569848

申请日：2016-04-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jun SUN ,  Zhongyu LIN ,  Guangyang WANG ,  Guipeng SUN

IPC: H01L27/02 ,  H01L29/78

CPC classification number: H01L27/0262 ,  H01L29/402 ,  H01L29/7817 ,  H01L29/87

Abstract: An electrostatic protection device of an LDMOS silicon controlled structure comprises a P-type substrate (310), an N-well (320) and a P-well (330) on the substrate, a gate electrode (340) overlapping on the P-well (330) and extending to an edge of the N-well (320), a first N+ structure and a first P+ structure provided in the N-well (320), and a second N+ structure and a second P+ structure provided in the P-well(330), the first N+ structure being a drain electrode N+ structure (322), the first N+ structure being a drain electrode N+ structure (322), the first P+ structure being a drain electrode P+ structure (324), the second N+ structure being a source electrode N+ structure (332), the second P+ structure being a source P+ structure (334), and a distance from the drain electrode P+ structure (324) to the gate electrode (340) being greater than a distance from the drain electrode N+ structure (322) to the gate electrode (340).

公开(公告)号：US20180114831A1

公开(公告)日：2018-04-26

申请号：US15564727

申请日：2016-01-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun QI

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/0634 ,  H01L29/0623 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/66568 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: A laterally diffused metal oxide semiconductor field-effect transistor, comprising a substrate (110), a source electrode (150), a drain electrode (140), a body region (160), and a well region on the substrate, the well region comprising: an insertion-type well (122) having P-type doping, being arranged below the drain electrode and being connected to the drain electrode; N wells (124), arranged on two sides of the insertion-type well; and P wells (126), arranged next to the N wells and being connected to the N wells; the source electrode and the body region are arranged in the P well.

公开(公告)号：US20180019159A1

公开(公告)日：2018-01-18

申请号：US15548257

申请日：2016-01-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Wei LI ,  Long HAO ,  Yan JIN

IPC: H01L21/762 ,  H01L21/265 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/0217 ,  H01L21/26513 ,  H01L21/28105 ,  H01L21/28123 ,  H01L29/4983

Abstract: A manufacturing method for a semiconductor device, comprising: providing a semiconductor substrate (100), and forming a shallow trench isolation structure (104) in the semiconductor substrate (100); forming a gate structure comprising a gate oxidation layer (105a) and a gate material layer (105b) that are stacked from the bottom up on the semiconductor substrate (100); executing first ion implantation so as to form first doping ions in the gate material layer (105b), and executing second ion implantation (109) so as to form second doping ions at the part of the gate material layer (105b) that is located over a top corner of the shallow trench isolation structure(104), the second doping ions and the first doping ions being opposite in conduction type.

公开(公告)号：US20180012980A1

公开(公告)日：2018-01-11

申请号：US15548290

申请日：2016-01-28

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yan GU ,  Wei SU ,  Sen ZHANG

IPC: H01L29/739 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/7394 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/735

Abstract: A lateral insulated gate bipolar transistor, comprising: a substrate (100), having a first conductivity type; an insulating layer (200), formed on the substrate (100); an epitaxial layer (300), having a second conductivity type and formed on the insulating layer (200); a field oxide layer (400), formed on the epitaxial layer (300); a first well (500), having the first conductivity type; a plurality of gate trench structures (600); second source doped regions (720), having the second conductivity type; first source doped regions (710), having the first conductivity type; a second well (800), having the second conductivity type; a first drain doped region (910), having the first conductivity type and formed on a surface layer of the second well (800); gate lead-out ends (10); a source lead-out end (20); a drain lead-out end (30).

公开(公告)号：US20140145354A1

公开(公告)日：2014-05-29

申请号：US14130482

申请日：2013-05-10

Applicant: CSMC Technologies Fab2 Co., Ltd.

Inventor： Xin Yang

IPC: H01L23/544

CPC classification number: H01L23/544 ,  G03F7/20 ,  G03F9/708 ,  H01L21/00 ,  H01L2223/54433 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fabrication method for semiconductor devices is provided. The method comprises: depositing a dielectric layer that includes a plurality of functional layers, and forming a contact hole, or through hole, and a metal layer. The forming of the contact hole, or through hole, and the metal layer comprises performing photolithography on regions corresponding to a marking label for the photolithography of the dielectric layer and the metal layer. On at least one of the functional layers, the performing photolithography on regions corresponding to a marking label for the photolithography comprises limiting the photolithography to the metal layer thereof. A semiconductor device thus fabricated is also provided. The method and device do not affect the reading of the marking label, and also can avoid the problem of defocusing in the vicinity of the marking label.

Abstract translation: 提供了半导体器件的制造方法。 该方法包括：沉积包括多个功能层的介电层，以及形成接触孔或通孔以及金属层。 接触孔或通孔以及金属层的形成包括在对应于用于电介质层和金属层的光刻的标记标签的区域上进行光刻。 在至少一个功能层上，对应于用于光刻的标记标签的区域上的执行光刻包括将光刻限制到其金属层。 还提供了如此制造的半导体器件。 该方法和装置不影响标记标签的读数，也可以避免标记标签附近散焦的问题。