公开(公告)号：US08994138B2

公开(公告)日：2015-03-31

申请号：US13710260

申请日：2012-12-10

Applicant: STMicroelectronics S.A. ,  STMicroelectronics (Crolles2) SAS

Inventor： François Roy ,  Sebastien Place

IPC: H01L27/146 ,  H01L31/18 ,  H04N5/76

CPC classification number: H01L27/14643 ,  H01L27/1461 ,  H01L27/1463 ,  H01L31/18 ,  H04N5/76

Abstract: An image sensor including a pixel array, each pixel including, in a substrate of a doped semiconductor material of a first conductivity type, a first doped region of a second conductivity type at the surface of the substrate; an insulating trench surrounding the first region; a second doped region of the first conductivity type, more heavily doped than the substrate, at the surface of the substrate and surrounding the trench; a third doped region of the second conductivity type, forming with the substrate a photodiode junction, extending in depth into the substrate under the first and second regions and being connected to the first region; and a fourth region, more lightly doped than the second and third regions, interposed between the second and third regions and in contact with the first region and/or with the third region.

Abstract translation: 一种图像传感器，包括像素阵列，每个像素包括在第一导电类型的掺杂半导体材料的衬底中，在衬底的表面处具有第二导电类型的第一掺杂区域; 围绕所述第一区域的绝缘沟槽; 第一导电类型的第二掺杂区域，在衬底的表面上比衬底更重掺杂并且围绕沟槽; 第二导电类型的第三掺杂区域，与衬底一起形成光电二极管结，在第一和第二区域下方深度延伸到衬底中，并连接到第一区域; 以及介于所述第二和第三区域之间并与所述第一区域和/或与所述第三区域接触的比所述第二和第三区域更轻掺杂的第四区域。

公开(公告)号：US08928051B2

公开(公告)日：2015-01-06

申请号：US14084803

申请日：2013-11-20

Applicant: International Business Machines Corporation ,  STMicroelectronics S.A.

Inventor： Erwan Dornel ,  Pascal R. Tannhof ,  Denis Rideau

IPC: H01L29/40 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/401 ,  H01L21/28247 ,  H01L29/42368 ,  H01L29/51 ,  H01L29/512 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of fabricating a semiconductor device including providing a gate structure on a channel portion of a semiconductor substrate, wherein the gate structure includes at least one gate dielectric on the channel portion of the semiconductor substrate and at least one gate conductor on the at least one gate dielectric. An edge portion of the at least one gate dielectric is removed on each side of the gate structure, wherein the removing of the edge portion of the gate dielectric provides an exposed base edge of the at least one gate conductor and an exposed channel surface of the semiconductor substrate underlying the gate structure. The sidewall of the gate structure is oxidized, which also oxidizes at least one of the exposed base edge of the at least one gate conductor and the exposed channel surface of the semiconductor substrate that is underlying the gate structure.

Abstract translation: 一种制造半导体器件的方法，包括在半导体衬底的沟道部分上提供栅极结构，其中栅极结构包括在半导体衬底的沟道部分上的至少一个栅极电介质和至少一个栅极导体 栅电介质。 所述至少一个栅极电介质的边缘部分在所述栅极结构的每一侧被去除，其中去除所述栅极电介质的所述边缘部分提供所述至少一个栅极导体的暴露的基极边缘和所述至少一个栅极导体的暴露的沟道表面 栅极结构底层的半导体衬底。 栅极结构的侧壁被氧化，其还氧化至少一个栅极导体的暴露的基极边缘和位于栅极结构下方的半导体衬底的暴露的沟道表面中的至少一个。

公开(公告)号：US20140347907A1

公开(公告)日：2014-11-27

申请号：US14280955

申请日：2014-05-19

Applicant: STMicroelectronics S.A.

Inventor： Olivier Menut ,  David Turgis ,  Lorenzo Ciampolini

IPC: G11C15/04

CPC classification number: G11C15/046 ,  G11C15/04

Abstract: Electronic component including a ternary content-addressable memory component, configured to compare the input data items with a set of pre-recorded reference data words; the memory component incorporates a matrix of elementary cells arranged in lines and columns; each line incorporates cells in each of which is recorded one bit of one of the reference data words; the cells of a given column are dedicated to the comparison of the same bit of the input data word; each cell incorporates: two memory points storing the data representing the reference data bit; a comparison circuit connected to the memory points, with a comparison point of which the potential represents the comparison if the input data bit and the data stored in the memory points, and also incorporating a common comparison circuit to which are connected the comparison circuits of all or part of the cells of a given column; the comparison circuit incorporates terminals to which the bit from the input data word and its complement are applied.

Abstract translation: 电子部件，包括三元内容可寻址存储器部件，被配置为将输入数据项与一组预先记录的参考数据字进行比较; 存储器组件包含以行和列布置的基本单元矩阵; 每行包含单元，每个单元记录一个参考数据字的一位; 给定列的单元专门用于比较输入数据字的相同位; 每个单元包含：存储表示参考数据位的数据的两个存储点; 连接到存储点的比较电路，如果输入数据位和存储在存储点中的数据，电位代表比较的比较点，并且还结合有公共比较电路，连接到所有比较电路的所有比较电路 或给定色谱柱的一部分细胞; 比较电路结合了来自输入数据字及其补码的位的终端。

公开(公告)号：US20140124866A1

公开(公告)日：2014-05-08

申请号：US13853111

申请日：2013-03-29

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS S.A.

Inventor： Philippe Galy ,  Patrice Dehan ,  Boris Heitz ,  Jean Jimenez

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L27/0727 ,  H01L29/41775 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66643 ,  H01L29/7839

Abstract: An integrated circuit may include at least one MOS transistor having a sigmoid response. The at least one MOS transistor may include a substrate, a source region, a drain region, a gate region, and insulating spacer regions on either side of the gate region. The substrate may include a first region situated under the gate region between the insulating spacer regions. At least one of the source and drain regions may be separated from the first region of the substrate by a second region of the substrate situated under an insulating spacer region, which may be of a same type of conductivity as the first region of the substrate.

Abstract translation: 集成电路可以包括具有S形响应的至少一个MOS晶体管。 至少一个MOS晶体管可以包括栅极区域的任一侧上的衬底，源极区域，漏极区域，栅极区域和绝缘间隔区域。 衬底可以包括位于绝缘间隔区之间的栅极区域下方的第一区域。 源极和漏极区域中的至少一个可以通过位于绝缘间隔区域下方的衬底的第二区域与衬底的第一区域分离，绝缘间隔区域可以具有与衬底的第一区域相同类型的导电性。

公开(公告)号：US20140015102A1

公开(公告)日：2014-01-16

申请号：US13935813

申请日：2013-07-05

Applicant: STMicroelectronics S.A.

Inventor： Pierre Bar ,  Sylvain Joblot

IPC: H01L49/02

CPC classification number: H01L28/92 ,  H01L27/0207 ,  H01L27/0805 ,  H01L28/91

Abstract: A semiconductor device includes a substrate wafer and having a front face and a back face. A front hole is formed in the front face and a multilayer capacitor is formed in the front hole. A back hole is formed in the back face of the substrate wafer to expose at least a portion of the multilayer capacitor. A front electrical connection on the front face and a back electrical connection in the back hole are used to make electrical connection to first and second conductive plates of the multilayer capacitor which are separated by a dielectric layer. The front hole may have a cylindrical shape or an annular shape.

Abstract translation: 半导体器件包括具有正面和背面的衬底晶片。 在前面形成有前孔，在前孔中形成有层叠电容器。 在基板晶片的背面形成有后孔，露出至少一部分多层电容器。 使用前表面上的前电连接和后孔中的背电连接来与层叠电容器的由电介质层隔开的第一和第二导电板电连接。 前孔可以具有圆柱形或环形。

公开(公告)号：US20140004644A1

公开(公告)日：2014-01-02

申请号：US13858481

申请日：2013-04-08

Applicant: STMicroelectronics S.A. ,  STMicroelectronics (Crolles 2) SAS

Inventor： François Roy ,  Lucile Broussous ,  Julien Michelot ,  Jean-Pierre Oddou

IPC: H01L31/18

CPC classification number: H01L31/18 ,  H01L27/14605

Abstract: A method for manufacturing an image sensor, including the successive steps of: forming columns of a semiconductor material; forming one or several pixels at a first end of each of the columns; and deforming the structure so that the second ends of each of the columns come closer to each other or draw away from each other to form a surface in the shape of a polyhedral cap.

Abstract translation: 一种用于制造图像传感器的方法，包括以下连续步骤：形成半导体材料的列; 在每个列的第一端形成一个或几个像素; 并且使结构变形，使得每个柱的第二端彼此靠近或彼此拉开，以形成多面体盖的形状的表面。

公开(公告)号：US20130193550A1

公开(公告)日：2013-08-01

申请号：US13751489

申请日：2013-01-28

Applicant: STMicroelectronics S.A. ,  Commissariat a l'Energie Atomique et aux Energies Alternatives

Inventor： Benoit Sklenard ,  Perrine Batude

IPC: H01L23/58 ,  H01L21/02

CPC classification number: H01L23/585 ,  H01L21/02038 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing an integrated circuit, including the steps of forming first transistors on a first semiconductor layer; depositing a first insulating layer above the first semiconductor layer and the first transistors, and leveling the first insulating layer; depositing a conductive layer above the first insulating layer, and covering the conductive layer with a second insulating layer; bonding a semiconductor wafer to the second insulating layer; thinning the semiconductor wafer to obtain a second semiconductor layer; and forming second transistors on the second semiconductor layer.

Abstract translation: 一种用于制造集成电路的方法，包括以下步骤：在第一半导体层上形成第一晶体管; 在所述第一半导体层和所述第一晶体管之上沉积第一绝缘层，以及对所述第一绝缘层进行调平; 在第一绝缘层上方沉积导电层，并用第二绝缘层覆盖导电层; 将半导体晶片接合到所述第二绝缘层; 使半导体晶片变薄以获得第二半导体层; 以及在所述第二半导体层上形成第二晶体管。

公开(公告)号：US20130157587A1

公开(公告)日：2013-06-20

申请号：US13707736

申请日：2012-12-07

Applicant: STMICROELECTRONICS S.A.

Inventor： Floria Blanchet ,  Christophe Arricastres ,  Denis Pache

IPC: H01F5/00

CPC classification number: H01F5/003 ,  H01F21/12 ,  H01F27/2804 ,  H01F30/04 ,  H01L23/5227 ,  H01L23/66 ,  H01L27/01 ,  H01L28/10 ,  H01L2223/6655 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01P5/10 ,  H03H7/1775 ,  H03H7/42 ,  H01L2924/00

Abstract: An integrated circuit includes an integrated transformer of the balanced-to-unbalanced type with N channels, wherein N is greater than 2. The integrated transformer includes, on a substrate, N inductive circuits that are mutually inductively coupled, and respectively associated with N channels.

Abstract translation: 集成电路包括具有N个通道的平衡不平衡型的集成变压器，其中N大于2.集成变压器在衬底上包括相互感应耦合并且分别与N个通道相关联的N个感应电路 。

公开(公告)号：US20130155558A1

公开(公告)日：2013-06-20

申请号：US13705503

申请日：2012-12-05

Applicant: STMicroelectronics S.A.

Inventor： Johan Bourgeat ,  Philippe Galy

IPC: H02H9/04

CPC classification number: H01L23/60 ,  H01L27/0262 ,  H01L27/0274 ,  H01L27/0296 ,  H01L29/0692 ,  H01L29/747 ,  H01L2924/0002 ,  H02H9/04 ,  H01L2924/00

Abstract: A device for protecting a set of N nodes from electrostatic discharges, wherein N is greater than or equal to three, includes a set of N units respectively possessing N first terminals respectively connected to the N nodes and N second terminals connected together to form a common terminal. Each unit includes at least one MOS transistor including a parasitic transistor connected between a pair of the N nodes and configured, in the presence of a current pulse between the pair of nodes, to operate, at least temporarily, in a hybrid mode including MOS-type operation in a sub-threshold mode and operation of the bipolar transistor.

Abstract translation: 用于保护一组N个节点免受静电放电的装置，其中N大于或等于3，包括分别具有分别连接到N个节点的N个第一终端的N个单元的集合和连接在一起的N个第二终端以形成公共 终奌站。 每个单元包括至少一个MOS晶体管，其包括连接在一对N个节点之间的寄生晶体管，并且在所述一对节点之间存在电流脉冲的情况下，配置为至少临时地以包括MOS- 在亚阈值模式下工作和双极晶体管的工作。

公开(公告)号：US20130155283A1

公开(公告)日：2013-06-20

申请号：US13710260

申请日：2012-12-10

Applicant: STMicroelectronics S.A. ,  STMicroelectronics (Crolles2) SAS

Inventor： François Roy ,  Sebastien Place

IPC: H01L27/146 ,  H04N5/76 ,  H01L31/18

CPC classification number: H01L27/14643 ,  H01L27/1461 ,  H01L27/1463 ,  H01L31/18 ,  H04N5/76

Abstract: An image sensor including a pixel array, each pixel including, in a substrate of a doped semiconductor material of a first conductivity type, a first doped region of a second conductivity type at the surface of the substrate; an insulating trench surrounding the first region; a second doped region of the first conductivity type, more heavily doped than the substrate, at the surface of the substrate and surrounding the trench; a third doped region of the second conductivity type, forming with the substrate a photodiode junction, extending in depth into the substrate under the first and second regions and being connected to the first region; and a fourth region, more lightly doped than the second and third regions, interposed between the second and third regions and in contact with the first region and/or with the third region.

Abstract translation: 一种图像传感器，包括像素阵列，每个像素包括在第一导电类型的掺杂半导体材料的衬底中，在衬底的表面处具有第二导电类型的第一掺杂区域; 围绕所述第一区域的绝缘沟槽; 第一导电类型的第二掺杂区域，在衬底的表面上比衬底更重掺杂并且围绕沟槽; 第二导电类型的第三掺杂区域，与衬底一起形成光电二极管结，在第一和第二区域下方深度延伸到衬底中，并连接到第一区域; 以及介于所述第二和第三区域之间并与所述第一区域和/或与所述第三区域接触的比所述第二和第三区域更轻掺杂的第四区域。