公开(公告)号：US20250022931A1

公开(公告)日：2025-01-16

申请号：US18779444

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Yeh CHEN ,  Wei-Yang LEE ,  Chia-Pin LIN ,  Da-Wen LIN

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer.

公开(公告)号：US20250022763A1

公开(公告)日：2025-01-16

申请号：US18352363

申请日：2023-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Han Tsai ,  Tsung-Yu Chen ,  Hong-Yu Guo ,  Tsung-Shu Lin

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/29 ,  H01L25/10

Abstract: Semiconductor device and methods of manufacture are provided. In an embodiment, the a semiconductor device may include a first semiconductor die; an oxide layer on the first semiconductor die, wherein the first semiconductor die has a first top surface opposite the oxide layer; a first insulating material encapsulating the first semiconductor die and the oxide layer, wherein the first insulating material has a second top surface planar with the first top surface; and a first polymer buffer disposed between a sidewall of the first semiconductor die and a sidewall of the oxide layer, wherein the first polymer buffer has a third top surface planar with both the first top surface and the second top surface.

公开(公告)号：US12199158B2

公开(公告)日：2025-01-14

申请号：US18178644

申请日：2023-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Ho Lin ,  Chun-Heng Chen ,  Xiong-Fei Yu ,  Chi On Chui

IPC: H01L21/76 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a fin protruding over a substrate; forming a conformal oxide layer over an upper surface and along sidewalls of the fin; performing an anisotropic oxide deposition or an anisotropic plasma treatment to form a non-conformal oxide layer over the upper surface and along the sidewalls of the fin; and forming a gate electrode over the fin, the conformal oxide layer and the non-conformal oxide layer being between the fin and the gate electrode.

公开(公告)号：US12198953B2

公开(公告)日：2025-01-14

申请号：US18338981

申请日：2023-06-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Rong Xiao ,  Wei-Hsiang Huang ,  Sen-Yeo Peng ,  Chui-Ya Peng

IPC: H01L21/67

Abstract: A system includes a cooler, a concentration meter, a first pump and a second pump. The cooler is configured to cool first liquid by second liquid in the cooler. The concentration meter is configured to measure a concentration of the first liquid. The first pump is configured to move the first liquid according to the concentration. The second pump is coupled to the cooler, disposed with the first pump in a parallel manner, and configured to move the second liquid.

公开(公告)号：US12197138B2

公开(公告)日：2025-01-14

申请号：US17185827

申请日：2021-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Cheng Lin ,  Chien Rhone Wang ,  Kewei Zuo ,  Ming-Tan Lee ,  Zi-Jheng Liu

IPC: G03F7/00 ,  G06F30/27 ,  G06F30/398 ,  G06N20/00

Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and machine learning are used to train a classification that correlates the overlay error source factors with overlay metrology categories. The overlay error source factors include tool signals. The trained classification includes a base classification and a Meta classification.

公开(公告)号：US12191393B2

公开(公告)日：2025-01-07

申请号：US17239328

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yan-Ting Lin ,  Yen-Ru Lee ,  Chien-Chang Su ,  Chih-Yun Chin ,  Chien-Wei Lee ,  Pang-Yen Tsai ,  Chii-Horng Li ,  Yee-Chia Yeo

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A nano-FET and a method of forming is provided. In some embodiments, a nano-FET includes an epitaxial source/drain region contacting ends of a first nanostructure and a second nanostructure. The epitaxial source/drain region may include a first semiconductor material layer of a first semiconductor material, such that the first semiconductor material layer includes a first segment contacting the first nanostructure and a second segment contacting the second nanostructure, wherein the first segment is separated from the second segment. A second semiconductor material layer is formed over the first segment and the second segment. The second semiconductor material layer may include a second semiconductor material having a higher concentration of dopants of a first conductivity type than the first semiconductor material layer. The second semiconductor material layer may have a lower concentration percentage of silicon than the first semiconductor material layer.

公开(公告)号：US12191222B2

公开(公告)日：2025-01-07

申请号：US18335294

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Chen ,  Sih-Hao Liao ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L23/31 ,  H01L23/498

Abstract: A redistribution structure is made using filler-free insulating materials with a high shrinkage rate. As a result, good planarity may be achieved without the need to perform a planarization of each insulating layer of the redistribution structure, thereby simplifying the formation of the redistribution structure.

公开(公告)号：US12191206B2

公开(公告)日：2025-01-07

申请号：US17353213

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a gate stack on a plurality of semiconductor fins. The plurality of semiconductor fins includes a plurality of inner fins, and a first outer fin and a second outer fin on opposite sides of the plurality of inner fins. Epitaxy regions are grown based on the plurality of semiconductor fins, and a first height of the epitaxy regions measured along an outer sidewall of the first outer fin is smaller than a second height of the epitaxy regions measured along an inner sidewall of the first outer fin.

公开(公告)号：US12191174B2

公开(公告)日：2025-01-07

申请号：US17720807

申请日：2022-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chih-Kai Yang ,  Chun-Liang Chen ,  Wei-Ting Chien ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/67 ,  G03F7/40

Abstract: In an embodiment, a pattern transfer processing chamber includes a pattern transfer processing chamber and a loading area external to the pattern transfer processing chamber. The loading area is configured to transfer a wafer to or from the pattern transfer processing chamber. The loading area comprises a first region including a loadport, a second region including a load-lock between the first region and the pattern transfer processing chamber, and an embedded baking chamber configured to heat a patterned photoresist on the wafer.

公开(公告)号：US12190036B2

公开(公告)日：2025-01-07

申请号：US18447170

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Pin Chou ,  Chun-Wen Wang ,  Meng Ku Chi ,  Yan-Cheng Chen ,  Jun-Xiu Liu

IPC: G06F30/367 ,  G06N5/04 ,  G06N20/00 ,  G06T7/00 ,  G06T7/70

Abstract: A semiconductor wafer defect detection system captures test images of a semiconductor wafer. The system analyzes the test images with an analysis model trained with a machine learning process. The analysis model generates simulated integrated circuit layouts based on the test images. The system detects defects in the semiconductor wafer by comparing the simulated integrated circuit layouts to reference integrated circuit layouts.