公开(公告)号：US20050146199A1

公开(公告)日：2005-07-07

申请号：US10750764

申请日：2004-01-05

Applicant: Wen-Chin Lee

Inventor： Wen-Chin Lee

IPC: B28D1/18 ,  E21C25/10 ,  E21C35/18

CPC classification number: B28D1/188 ,  E21C2035/1806

Abstract: A rotatable cutting tool for applications such as road resurfacing work includes a cutting bit insert and a tool body. The cutting bit insert includes an insert body and an inner tiered protrusion integrally formed from the insert body. The inner tiered protrusion has multiple tiers. The tool body has a tiered recess that corresponds to the inner tiered protrusion to hold the inner tiered protrusion. A combination of the inner tiered protrusion and the tiered recess provides a strong connection for the cutting bit insert and the tool body and keeps stress from concentrating at a single point.

Abstract translation: 用于诸如道路重铺工作的应用的可旋转切削工具包括切削钻头刀片和刀具本体。 刀头刀片包括插入体和从插入体整体形成的内层突起。 内层突起具有多层。 工具主体具有对应于内层突起以保持内层突起的分层凹部。 内层突起和分层凹槽的组合为切削钻头刀片和工具主体提供了强大的连接，并且使应力集中在单个点处。

公开(公告)号：US20050093067A1

公开(公告)日：2005-05-05

申请号：US10999564

申请日：2004-11-29

Applicant: Yee-Chia Yeo ,  How-Yu Chen ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Fu-Liang Yang ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  How-Yu Chen ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Fu-Liang Yang ,  Chenming Hu

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7854

Abstract: In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.

公开(公告)号：US20050035369A1

公开(公告)日：2005-02-17

申请号：US10729092

申请日：2003-12-05

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/11 ,  H01L29/78 ,  H01L31/0328

CPC classification number: H01L29/6653 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/1104 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7842 ,  H01L29/7848

Abstract: A semiconductor device or circuit is formed on a semiconductor substrate with first and second semiconductor materials having different lattice-constants. A first transistor includes a channel region formed oppositely adjacent a source and drain region. At least a portion of the source and drain regions are formed in the second semiconductor material thereby forming lattice-mismatched zones in the first transistor. A second component is coupled to the transistor to form a circuit, e.g., an inverter. The second component can be a second transistor having a conductivity type differing from the first transistor or a resistor.

Abstract translation: 半导体器件或电路在具有不同晶格常数的第一和第二半导体材料的半导体衬底上形成。 第一晶体管包括与源区和漏区相对地形成的沟道区。 源区和漏区的至少一部分形成在第二半导体材料中，从而在第一晶体管中形成晶格失配区。 第二分量耦合到晶体管以形成电路，例如逆变器。 第二部件可以是具有不同于第一晶体管或电阻器的导电类型的第二晶体管。

公开(公告)号：US08569837B2

公开(公告)日：2013-10-29

申请号：US11800615

申请日：2007-05-07

Applicant: Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Ta-Ming Kuan ,  Wen-Chin Lee

Inventor： Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Ta-Ming Kuan ,  Wen-Chin Lee

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a deep source/drain region adjacent the gate electrode; a silicide region over the deep source/drain region; and an elevated metallized source/drain region between the silicide region and the gate electrode. The elevated metallized source/drain region adjoins the silicide region.

Abstract translation: 半导体结构包括半导体衬底; 半导体衬底上的栅极电介质; 位于栅极电介质上的栅电极; 与栅电极相邻的深源/漏区; 深源/漏区上的硅化物区; 以及在硅化物区域和栅电极之间的升高的金属化源极/漏极区域。 升高的金属化源极/漏极区域邻接硅化物区域。

公开(公告)号：US08546176B2

公开(公告)日：2013-10-01

申请号：US12765407

申请日：2010-04-22

Applicant: Wen-Chin Lee ,  Wen-Tsai Yen ,  Ding-Yuan Chen ,  Liang-Sheng Yu ,  Yu-Han Chang

Inventor： Wen-Chin Lee ,  Wen-Tsai Yen ,  Ding-Yuan Chen ,  Liang-Sheng Yu ,  Yu-Han Chang

IPC: H01L21/00

CPC classification number: C23C14/3464 ,  C23C14/0623 ,  H01L31/0322 ,  Y02E10/541 ,  Y02P70/521

Abstract: Sulfur-containing chalcogenide absorbers in thin film solar cell are manufactured by sequential sputtering or co-sputtering targets, one of which contains a sulfur compound, onto a substrate and then annealing the substrate. The anneal is performed in a non-sulfur containing environment and avoids the use of hazardous hydrogen sulfide gas. A sulfurized chalcogenide is formed having a sulfur concentration gradient.

Abstract translation: 在薄膜太阳能电池中的含硫硫属元素化物吸收剂通过在衬底上顺序溅射或共溅射靶（其中一个含有硫化合物）然后对衬底进行退火来制造。 退火在不含硫的环境中进行，避免使用危险的硫化氢气体。 形成具有硫浓度梯度的硫化硫族化物。

公开(公告)号：US20130167916A1

公开(公告)日：2013-07-04

申请号：US13338292

申请日：2011-12-28

Applicant: Wen-Chin LEE ,  Liang-Sheng YU

Inventor： Wen-Chin LEE ,  Liang-Sheng YU

IPC: H01L31/0352 ,  H01L31/18

CPC classification number: H01L31/0749 ,  H01L31/02363 ,  H01L31/0322 ,  H01L31/035281 ,  H01L31/03923 ,  H01L31/046 ,  H01L31/0465 ,  Y02E10/541

Abstract: A thin film photovoltaic cell and method for forming the same. The thin film photovoltaic cell includes a first electrode layer formed on a substrate. An absorber layer of a first dopant-type is formed on the first electrode layer. The absorber layer has an opening extending partially into the absorber layer from a top surface of the absorber layer. The opening has side walls and a bottom surface. A buffer layer of a second dopant type is formed on the top surface of the absorber layer, the side walls of the opening and the bottom surface of the opening A second electrode layer is formed on the buffer layer.

Abstract translation: 一种薄膜光伏电池及其形成方法。 薄膜光伏电池包括形成在基板上的第一电极层。 第一掺杂剂型的吸收层形成在第一电极层上。 吸收层具有从吸收体层的上表面部分地延伸到吸收体层中的开口。 开口具有侧壁和底面。 在吸收体层的顶面形成有第二掺杂剂型的缓冲层，在缓冲层上形成开口侧壁和开口底面第二电极层。

公开(公告)号：US08466505B2

公开(公告)日：2013-06-18

申请号：US11077479

申请日：2005-03-10

Applicant: Li-Shyue Lai ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

Inventor： Li-Shyue Lai ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

IPC: H01L29/788

CPC classification number: H01L21/28273 ,  H01L29/66825 ,  H01L29/7391 ,  H01L29/8616

Abstract: A semiconductor device and a method of forming the same. The semiconductor device comprises a gate structure comprising a tunnel oxide over a substrate; a floating gate over the tunnel oxide; a dielectric over the floating gate; and a control gate over the dielectric. The semiconductor device further comprises: spacers along opposite edges of the gate structure; a first impurity region doped with a first type of dopant laterally spaced apart from a first edge of the gate structure; and a second impurity region doped with a second type of dopant, opposite from the first type, the drain being substantially under the drain spacer and substantially aligned with a second edge of the gate structure.

Abstract translation: 一种半导体器件及其制造方法。 半导体器件包括栅极结构，其包括在衬底上的隧道氧化物; 隧道氧化物上的浮动栅; 在浮动栅极上的电介质; 以及电介质上的控制栅极。 半导体器件还包括：沿着栅极结构的相对边缘的间隔物; 掺杂有与栅极结构的第一边缘横向间隔开的第一类型掺杂物的第一杂质区; 以及掺杂有与第一类型相反的第二类型掺杂剂的第二杂质区，漏极基本上在漏极间隔下方并且基本上与栅极结构的第二边缘对准。

公开(公告)号：US08426298B2

公开(公告)日：2013-04-23

申请号：US13113530

申请日：2011-05-23

Applicant: Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

Inventor： Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC: H01L21/28 ,  H01L21/44

CPC classification number: H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/47 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/66643 ,  H01L29/7843

Abstract: A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device is reduced by forming the PMOS device over a semiconductor layer having a low valence band.

Abstract translation: 半导体结构包括半导体衬底和在半导体衬底的表面处的NMOS器件，其中NMOS器件包括肖特基源/漏延伸区域。 半导体结构还包括在半导体衬底的表面处的PMOS器件，其中PMOS器件包括仅包含非金属材料的源极/漏极延伸区域。 可以为PMOS器件和NMOS器件形成肖特基源极/漏极延伸区域，其中通过在具有低价带的半导体层上形成PMOS器件来减小PMOS器件的肖特基势垒高度。

公开(公告)号：US20120237721A1

公开(公告)日：2012-09-20

申请号：US13461006

申请日：2012-05-01

Applicant: CHENG-HSIEN LIN ,  YAO-WEN BAI ,  WEN-CHIN LEE ,  RUI ZHANG ,  KAI-LI JIANG ,  CHEN FENG

Inventor： CHENG-HSIEN LIN ,  YAO-WEN BAI ,  WEN-CHIN LEE ,  RUI ZHANG ,  KAI-LI JIANG ,  CHEN FENG

IPC: B32B5/12 ,  B82Y30/00

CPC classification number: H05K9/009 ,  B29C70/882 ,  B29C70/885 ,  B29K2105/167 ,  C08L2666/76 ,  H05K9/0083 ,  H05K9/0088 ,  Y10S977/784 ,  Y10S977/789 ,  Y10T428/24132 ,  Y10T428/249979

Abstract: An electromagnetic shielding composite includes a polymer and a carbon nanotube film structure. The carbon nanotube structure includes a number of carbon nanotubes disposed in the polymer. The number of carbon nanotubes are parallel with each other.

Abstract translation: 电磁屏蔽复合材料包括聚合物和碳纳米管薄膜结构。 碳纳米管结构包括设置在聚合物中的多个碳纳米管。 碳纳米管的数量彼此平行。

公开(公告)号：US08084305B2

公开(公告)日：2011-12-27

申请号：US12036616

申请日：2008-02-25

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chung-Hu Ke

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chung-Hu Ke

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L29/66772 ,  H01L27/1203 ,  H01L29/78618 ,  Y10S257/90

Abstract: A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.

Abstract translation: 半导体器件包括覆盖介电层的半导体台面，形成在半导体台面上的栅叠层，以及形成在半导体台面周围的隔离间隔物，并填充半导体台面的边缘处的任何底切区域。