公开(公告)号：US20190181866A1

公开(公告)日：2019-06-13

申请号：US16148977

申请日：2018-10-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: H03K19/0944 ,  H03K19/20

CPC classification number: H03K19/0944 ,  H03K19/20

Abstract: A combinational logic circuit includes input circuitry to receive a first input signal that transitions between upper and lower voltages of a first voltage domain, and to generate, in response to the transitions of the first input signal, a first localized signal that transitions between upper and lower voltages of a second voltage domain. The combinational logic circuit additionally includes output circuitry to generate a first output signal that transitions between the upper and lower supply voltages of the first voltage domain based at least in part on the transitions of the first localized signal.

公开(公告)号：US20180351574A1

公开(公告)日：2018-12-06

申请号：US15973280

申请日：2018-05-07

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: H03M13/05 ,  G06F3/06 ,  G06F13/16 ,  H03M13/11 ,  H03M13/15 ,  H03M13/19 ,  H03M13/09

CPC classification number: H03M13/05 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0673 ,  G06F13/1668 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/19

Abstract: Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

公开(公告)号：US10146608B2

公开(公告)日：2018-12-04

申请号：US15090399

申请日：2016-04-04

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Catherine Chen ,  Scott C. Best ,  John Eric Linstadt ,  Frederick A. Ware

IPC: G06F11/07 ,  G11C29/44 ,  G06F13/00 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26

Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

公开(公告)号：US20180293130A1

公开(公告)日：2018-10-11

申请号：US15907210

申请日：2018-02-27

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent S. Haukness ,  John Eric Linstadt ,  Scott C. Best

IPC: G06F11/10 ,  G11C29/44 ,  G11C29/42 ,  G11C5/04 ,  G11C29/04

CPC classification number: G06F11/1048 ,  G11C5/04 ,  G11C29/42 ,  G11C29/44 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

公开(公告)号：US20180197596A1

公开(公告)日：2018-07-12

申请号：US15876539

申请日：2018-01-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Thomas Vogelsang

IPC: G11C11/4093 ,  G11C11/4094 ,  G11C11/4076

CPC classification number: G11C11/4093 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4097

Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.

公开(公告)号：US20180196767A1

公开(公告)日：2018-07-12

申请号：US15867646

申请日：2018-01-10

Applicant: Rambus Inc.

Inventor： John Eric Linstadt

IPC: G06F13/16 ,  G06F12/06 ,  G11C7/20 ,  G11C7/10 ,  G06F12/02 ,  G11C7/22

CPC classification number: G06F13/1694 ,  G06F12/0246 ,  G06F12/0623 ,  G06F12/0646 ,  G06F13/1678 ,  G06F2212/7206 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/20 ,  G11C7/22

Abstract: A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.

公开(公告)号：US09892068B2

公开(公告)日：2018-02-13

申请号：US14438865

申请日：2013-11-19

Applicant: Rambus Inc.

Inventor： John Eric Linstadt

IPC: G06F12/00 ,  G06F13/16 ,  G06F12/06 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G06F12/02

CPC classification number: G06F13/1694 ,  G06F12/0246 ,  G06F12/0623 ,  G06F12/0646 ,  G06F13/1678 ,  G06F2212/7206 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/20 ,  G11C7/22

Abstract: A memory controller (110) interfaces with one or more memory devices (120-n) having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices (120-n), the memory controller (110) automatically discovers the connectivity configuration of the one or more memory devices (120-n), including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller (110) configures the memory devices (120-n) according to the discovered connectivity and assigns unique addresses to jointly selected devices.

公开(公告)号：US20170337144A1

公开(公告)日：2017-11-23

申请号：US15525379

申请日：2015-11-11

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Craig E. Hampel ,  Scott C. Best ,  John Yan

IPC: G06F13/16

CPC classification number: G06F13/1678 ,  G06F13/1673 ,  G06F13/1694

Abstract: Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility, or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.

公开(公告)号：US20170285957A1

公开(公告)日：2017-10-05

申请号：US15629173

申请日：2017-06-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: G11C8/12 ,  G06F3/06 ,  G06F12/06

CPC classification number: G06F3/0604 ,  G06F3/0635 ,  G06F3/0673 ,  G06F12/06 ,  G06F2212/1048 ,  G11C8/12 ,  G11C2207/107

Abstract: A multiple memory rank selection method and system assigns, based at least in part on decoding an assignment signal in a second command/address signal, a first terminal of a memory device to receive a first command/address signal and a second terminal of the memory device to receive the second command/address signal or assigns the first terminal of the memory device to receive the second command/address signal and the second terminal of the memory device to receive the first command/address signal. The multiple memory selection method and system decodes a selection signal encoded in the first command/address signal and enables the memory device based at least in part on the assignment signal and the selection signal.

公开(公告)号：US09697884B2

公开(公告)日：2017-07-04

申请号：US15262741

申请日：2016-09-12

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/52

CPC classification number: G11C11/4093 ,  G06F11/1048 ,  G11C7/02 ,  G11C11/4096 ,  G11C29/52 ,  G11C2029/0411

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable, and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.