公开(公告)号：US20250078936A1

公开(公告)日：2025-03-06

申请号：US18810484

申请日：2024-08-20

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C16/26 ,  G11C16/34

Abstract: The present invention provides a method for accessing a flash memory module, wherein the method includes the steps of: using a first set of threshold voltages, a positively adjusted first set of threshold voltages and a negatively adjusted first set of threshold voltages to read the first logical page to obtain first readout information, second readout information and third readout information, respectively; selecting a second logical page of the physical page; using a second set of threshold voltage to read the second logical page to generate fourth readout information; adjusting the first set of threshold voltages to generate an adjusted first set of threshold voltages according to the first readout information, the second readout information, the third readout information and the fourth readout information; and using the adjusted first set of threshold voltages to read the first logical page of the flash memory module.

公开(公告)号：US20250077344A1

公开(公告)日：2025-03-06

申请号：US18810493

申请日：2024-08-20

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/10 ,  G06F13/16

Abstract: A flash memory controller, to be coupled between a host and a flash memory module, includes an error correction code (ECC) circuit. The ECC circuit performs a wordline-dimensional ECC operation upon specific data, sent from the host to form a super block stored within the flash memory module, to generate wordline-dimensional check code data and performs a finger-dimensional ECC operation upon the specific data generate finger-dimensional check code data. The ECC circuit corrects an error of the superblock by using the wordline-dimensional check code data and the finger-dimensional check code data so as to obtain correct data content of the specific data.

公开(公告)号：US12112809B2

公开(公告)日：2024-10-08

申请号：US18219083

申请日：2023-07-06

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/10 ,  G06F3/06 ,  G06F11/07 ,  G06F11/30 ,  G06F13/16 ,  G06F13/28 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34 ,  G11C29/52 ,  H03M13/15

CPC classification number: G11C16/26 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3427 ,  G11C29/52 ,  H03M13/152 ,  G11C16/0475 ,  G11C2211/5644 ,  G11C2211/5648

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

公开(公告)号：US11914873B2

公开(公告)日：2024-02-27

申请号：US17324121

申请日：2021-05-19

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

IPC: G11C7/00 ,  G06F3/06 ,  G06F12/02 ,  G11C11/56

CPC classification number: G06F3/0634 ,  G06F3/064 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0246 ,  G11C11/5628 ,  G11C11/5642 ,  G06F2212/7201 ,  G06F2212/7206 ,  Y02D10/00

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

公开(公告)号：US11881269B2

公开(公告)日：2024-01-23

申请号：US17302422

申请日：2021-05-03

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C16/26 ,  G11C16/06 ,  G11C16/34 ,  G11C16/04 ,  G11C16/16 ,  G11C16/10

CPC classification number: G11C16/26 ,  G11C16/04 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/10 ,  G11C16/16

Abstract: A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage. The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.

公开(公告)号：US11822428B2

公开(公告)日：2023-11-21

申请号：US17991799

申请日：2022-11-21

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C11/00 ,  G06F11/10 ,  G11C29/52 ,  G11C29/02 ,  G11C11/56 ,  G11C16/26 ,  H03M13/11 ,  G11C29/04

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C11/5642 ,  G11C16/26 ,  G11C29/028 ,  G11C29/52 ,  H03M13/1102 ,  G11C2029/0411

Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.

公开(公告)号：US11809713B1

公开(公告)日：2023-11-07

申请号：US17863383

申请日：2022-07-12

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0611 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0253 ,  G06F2212/7205

Abstract: A method for performing data access management of a memory device with aid of randomness-property control and associated apparatus are provided. The method may include: receiving a plurality of host commands from a host device and performing data access on the NV memory according to the plurality of host commands, for example, in response to at least one host write command, programming data into at least one single level cell (SLC) block to be first stored data corresponding to a data reception stage; and performing a seed-aware garbage collection (GC) procedure to collect valid data among the first stored data of the at least one SLC block into at least one non-SLC block to be second stored data corresponding to a data storage stage, for example, performing a randomness-property checking operation on multiple seeds to selectively determine respective data of multiple pages within the SLC block as target data.

公开(公告)号：US20230214320A1

公开(公告)日：2023-07-06

申请号：US17568690

申请日：2022-01-04

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F12/0253 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F2212/7201

Abstract: A method and apparatus for performing access control of a memory device with aid of additional physical address information are provided. The method includes: during a garbage collection procedure, reading valid data from a source block and writing the valid data into a destination block; updating at least one logical-to-physical address mapping table; receiving a first read request from a host device, wherein the first read request indicates reading at a first logical address; in response to the first read request, reading the valid data of the destination block according to the second physical address associated with the first logical address; receiving a second read request from the host device, wherein the second read request indicates reading at the first logical address; and in response to the second read request, reading the valid data of the source block according to the first physical address associated with the first logical address.

公开(公告)号：US11500722B2

公开(公告)日：2022-11-15

申请号：US17242326

申请日：2021-04-28

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu ,  Jian-Dong Du

IPC: G06F11/10 ,  G11C29/52 ,  G11C11/56 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

公开(公告)号：US11372718B2

公开(公告)日：2022-06-28

申请号：US17102442

申请日：2020-11-24

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/10 ,  G11C29/52 ,  G11C16/10 ,  G11C16/04

Abstract: The present invention provides a method for accessing a flash memory module, wherein the method comprises: receiving data and a corresponding metadata from a host device; performing a CRC operation upon the data to generate a CRC code; encoding the metadata and the CRC code to generate an adjusted parity code; encoding the data and the adjusted parity code to generate encoded data, wherein the encoded data comprises the data, the adjusted parity code and an error correction code corresponding to the data and the adjusted parity code; and writing the encoded data and the metadata to a page of a block of a flash memory module.