公开(公告)号：US20160276357A1

公开(公告)日：2016-09-22

申请号：US15050309

申请日：2016-02-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Hieu Van Tran ,  Nhan Do

IPC: H01L27/115 ,  H01L29/78 ,  H01L29/66 ,  H01L27/105

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/1052 ,  H01L27/11551 ,  H01L29/0847 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7856 ,  H01L29/7881

Abstract: A non-volatile memory cell including a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.

Abstract translation: 一种非易失性存储单元，包括具有上表面和两个侧表面的鳍形上表面的半导体衬底。 源极和漏极区域形成在鳍状上表面部分中，其间具有沟道区域。 导电浮栅包括沿着顶表面的第一部分延伸的第一部分，以及分别沿两个侧表面的第一部分延伸的第二和第三部分。 导电控制栅极包括沿着顶表面的第二部分延伸的第一部分，分别沿两个侧表面的第二部分延伸的第二部分和第三部分，第一部分和第二部分， 以及分别延伸至少一些所述浮动栅极第二和第三部分的第五和第六部分。

公开(公告)号：US20160260728A1

公开(公告)日：2016-09-08

申请号：US15057590

申请日：2016-03-01

Applicant: Silicon Storage Technology, Inc.

Inventor： Chun-Ming Chen ,  Jeng-Wei Yang ,  Chien-Sheng Su ,  Man-Tang Wu ,  Nhan Do

IPC: H01L27/115 ,  H01L29/423

CPC classification number: H01L27/11531 ,  G11C16/0425 ,  H01L21/28273 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/66825

Abstract: A memory device and method including a semiconductor substrate with memory and logic device areas. A plurality of memory cells are formed in the memory area, each including first source and drain regions with a first channel region therebetween, a floating gate disposed over a first portion of the first channel region, a control gate disposed over the floating gate, a select gate disposed over a second portion of the first channel region, and an erase gate disposed over the source region. A plurality of logic devices formed in the logic device area, each including second source and drain regions with a second channel region therebetween, and a logic gate disposed over the second channel region. The substrate upper surface is recessed lower in the memory area than in the logic device area, so that the taller memory cells have an upper height similar to that of the logic devices.

Abstract translation: 一种存储器件和方法，包括具有存储器和逻辑器件区域的半导体衬底。 多个存储单元形成在存储区域中，每个存储单元包括第一源极和漏极区域，其间具有第一沟道区域，布置在第一沟道区域的第一部分上方的浮置栅极，设置在浮置栅极上的控制栅极， 设置在第一通道区域的第二部分上的选择栅极和设置在源极区域上的擦除栅极。 形成在逻辑器件区域中的多个逻辑器件，每个逻辑器件包括在其间具有第二沟道区域的第二源极和漏极区域以及设置在第二沟道区域上的逻辑门极。 衬底上表面在存储器区域中比在逻辑器件区域中凹陷更低，使得较高的存储器单元具有与逻辑器件类似的上部高度。

公开(公告)号：US20160218195A1

公开(公告)日：2016-07-28

申请号：US15002307

申请日：2016-01-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Man-Tang Wu ,  Jeng-Wei Yang ,  Chien-Sheng Su ,  Chun-Ming Chen ,  Nhan Do

IPC: H01L29/66 ,  H01L27/115

CPC classification number: H01L29/66537 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825

Abstract: A method of forming a memory device on a substrate having memory, LV and HV areas, including forming pairs of spaced apart memory stacks in the memory area, forming a first conductive layer over and insulated from the substrate, forming a first insulation layer on the first conductive layer and removing it from the memory and HV areas, performing a conductive material deposition to thicken the first conductive layer in the memory and HV areas, and to form a second conductive layer on the first insulation layer in the LV area, performing an etch to thin the first conductive layer in the memory and HV areas and to remove the second conductive layer in the LV area, removing the first insulation layer from the LV area, and patterning the first conductive layer to form blocks of the first conductive layer in the memory, LV and HV areas.

Abstract translation: 一种在具有存储器，LV和HV区域的衬底上形成存储器件的方法，包括在存储区域中形成间隔开的存储堆叠对，在衬底上形成第一导电层并与衬底绝缘，在第一绝缘层上形成第一绝缘层 第一导电层并将其从存储器和HV区域中移除，执行导电材料沉积以增厚存储器和HV区域中的第一导电层，并在LV区域的第一绝缘层上形成第二导电层， 蚀刻以使存储器和HV区域中的第一导电层变薄，并且去除LV区域中的第二导电层，从LV区域移除第一绝缘层，以及图案化第一导电层以形成第一导电层的块 记忆，LV和HV区域。

公开(公告)号：US09306039B2

公开(公告)日：2016-04-05

申请号：US14665079

申请日：2015-03-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Mandana Tadayoni ,  Nhan Do

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/788 ,  H01L29/423 ,  H01L29/778 ,  H01L21/28 ,  H01L27/115 ,  H01L29/78

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/1054 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66484 ,  H01L29/7781 ,  H01L29/7849 ,  H01L29/788

Abstract: A memory device, and method of make same, having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and a stressor region of embedded silicon carbide formed in the substrate underneath the second gate.

Abstract translation: 一种存储器件及其制造方法，具有第一导电类型的半导体材料的衬底，第二导电类型的衬底中的第一和第二间隔开的区域，衬底中的沟道区域，导电浮动 栅极覆盖并与衬底绝缘，其中浮置栅极至少部分地布置在第一区域和通道区域的第一部分之上，导电第二栅极横向邻近并与浮动栅极绝缘，其中第二栅极被布置 至少部分地覆盖并与沟道区的第二部分绝缘，以及形成在第二栅极下方的衬底中的嵌入碳化硅的应力区域。

公开(公告)号：US09276005B1

公开(公告)日：2016-03-01

申请号：US14560475

申请日：2014-12-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Nhan Do

IPC: H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792

Abstract: A memory cell includes source and drain regions in a substrate with a channel region therebetween, an erase gate over the source region, a floating gate over a first channel region portion, a control gate over the floating gate, and a wordline gate over a second channel region portion. A first logic device includes second source and drain regions in the substrate with a second channel region therebetween under a first logic gate. A second logic device includes third source and drain regions in the substrate with a third channel region therebetween under a second logic gate. The wordline gate and the first and second logic gates comprise the same conductive metal material. The second logic gate is insulated from the third channel region by first and second insulation. The first logic gate is insulated from the second channel region by the second insulation and not by the first insulation.

Abstract translation: 存储单元包括在其中具有沟道区域的衬底中的源极和漏极区域，源极区域上的擦除栅极，在第一沟道区域部分上的浮动栅极，浮置栅极上的控制栅极以及第二沟道区域上的字线栅极 通道区域部分。 第一逻辑器件包括衬底中的第二源极和漏极区域，在第一逻辑门之下具有第二沟道区域。 第二逻辑器件包括衬底中的第三源极和漏极区域，在第二逻辑门极之间具有第三沟道区域。 字线栅极和第一和第二逻辑门包括相同的导电金属材料。 第二逻辑门通过第一和第二绝缘与第三沟道区绝缘。 第一逻辑门通过第二绝缘而与第二沟道区绝缘，而不是通过第一绝缘。

公开(公告)号：US09275748B2

公开(公告)日：2016-03-01

申请号：US14190010

申请日：2014-02-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Steven Malcolm Lemke ,  Jinho Kim ,  Jong-Won Yoo ,  Alexander Kotov ,  Yuri Tkachev

IPC: G11C16/26 ,  G11C16/14 ,  G11C16/04 ,  H01L21/28 ,  H01L29/788 ,  H01L27/115 ,  H01L29/423

CPC classification number: G11C16/26 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7881

Abstract: A method of reading a memory device having rows and columns of memory cells formed on a substrate, where each memory cell includes spaced apart first and second regions with a channel region therebetween, a floating gate disposed over a first portion of the channel region, a select gate disposed over a second portion of the channel region, a control gate disposed over the floating gate, and an erase gate disposed over the first region. The method includes placing a small positive voltage on the unselected source lines, and/or a small negative voltage on the unselected word lines, during the read operation to suppress sub-threshold leakage and thereby improve read performance.

Abstract translation: 一种读取存储器件的方法，所述存储器件具有形成在衬底上的存储器单元的行和列，其中每个存储器单元包括间隔开的第一和第二区域，其间具有通道区域;布置在沟道区域的第一部分上的浮置栅极， 设置在通道区域的第二部分上的选择栅极，设置在浮置栅极上的控制栅极以及设置在第一区域上的擦除栅极。 该方法包括在读取操作期间在未选择的源极线上放置小的正电压和/或在未选择的字线上施加小的负电压以抑制亚阈值泄漏，从而提高读取性能。

公开(公告)号：US20150200278A1

公开(公告)日：2015-07-16

申请号：US14665079

申请日：2015-03-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Mandana Tadayoni ,  Nhan Do

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/1054 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66484 ,  H01L29/7781 ,  H01L29/7849 ,  H01L29/788

Abstract: A memory device, and method of make same, having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and a stressor region of embedded silicon carbide formed in the substrate underneath the second gate.

Abstract translation: 一种存储器件及其制造方法，具有第一导电类型的半导体材料的衬底，第二导电类型的衬底中的第一和第二间隔开的区域，衬底中的沟道区域，导电浮动 栅极覆盖并与衬底绝缘，其中浮置栅极至少部分地布置在第一区域和通道区域的第一部分之上，导电第二栅极横向邻近并与浮动栅极绝缘，其中第二栅极被布置 至少部分地覆盖并与沟道区的第二部分绝缘，以及形成在第二栅极下方的衬底中的嵌入碳化硅的应力区域。

公开(公告)号：US20140269062A1

公开(公告)日：2014-09-18

申请号：US14190010

申请日：2014-02-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Steven Malcolm Lemke ,  Jinho Kim ,  Jong-Won Yoo ,  Alexander Kotov ,  Yuri Tkachev

IPC: G11C16/26 ,  G11C16/14 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7881

Abstract: A method of reading a memory device having rows and columns of memory cells formed on a substrate, where each memory cell includes spaced apart first and second regions with a channel region therebetween, a floating gate disposed over a first portion of the channel region, a select gate disposed over a second portion of the channel region, a control gate disposed over the floating gate, and an erase gate disposed over the first region. The method includes placing a small positive voltage on the unselected source lines, and/or a small negative voltage on the unselected word lines, during the read operation to suppress sub-threshold leakage and thereby improve read performance.

Abstract translation: 一种读取存储器件的方法，所述存储器件具有形成在衬底上的存储器单元的行和列，其中每个存储器单元包括间隔开的第一和第二区域，其间具有通道区域;布置在沟道区域的第一部分上的浮置栅极， 设置在通道区域的第二部分上的选择栅极，设置在浮置栅极上的控制栅极以及设置在第一区域上的擦除栅极。 该方法包括在读取操作期间在未选择的源极线上放置小的正电压和/或在未选择的字线上施加小的负电压以抑制亚阈值泄漏，从而提高读取性能。

公开(公告)号：US20140264539A1

公开(公告)日：2014-09-18

申请号：US14191625

申请日：2014-02-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Hieu Van Tran ,  Chien-Sheng Su ,  Prateep Tuntasood

IPC: H01L27/115

CPC classification number: H01L21/76224 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: A memory device array with spaced apart parallel isolation regions formed in a semiconductor substrate, with an active region between each pair of adjacent isolation regions. Each isolation region includes a trench formed into the substrate surface and an insulation material formed in the trench. Portions of a top surface of the insulation material are recessed below the surface of the substrate. Each active region includes a column of memory cells each having spaced apart first and second regions with a channel region therebetween, a floating gate over a first channel region portion, and a select gate over a second channel region portion. The select gates are formed as continuous word lines extending perpendicular to the isolation regions and each forming the select gates for one row of the memory cells. Portions of each word line extend down into the trenches and disposed laterally adjacent to sidewalls of the trenches.

Abstract translation: 一种存储器件阵列，其具有形成在半导体衬底中的间隔开的平行隔离区域，在每对相邻隔离区域之间具有有源区域。 每个隔离区域包括形成在衬底表面中的沟槽和形成在沟槽中的绝缘材料。 绝缘材料的顶表面的部分凹陷在基底的表面下方。 每个有源区域包括一列存储单元，每个存储单元具有间隔开的第一和第二区域，其间具有通道区域，在第一沟道区域部分上的浮动栅极以及在第二沟道区域部分上的选择栅极。 选择栅极形成为垂直于隔离区域延伸的连续字线，并且每个形成用于一行存储器单元的选择栅极。 每个字线的一部分向下延伸到沟槽中并且横向设置成与沟槽的侧壁相邻。

公开(公告)号：US12283314B2

公开(公告)日：2025-04-22

申请号：US18644840

申请日：2024-04-24

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G11C11/54 ,  G06N3/045 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H10B41/30 ,  H10D30/68

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, fourth lines each electrically connect the drain regions in one of the memory cell columns, and a plurality of transistors each electrically connected in series with one of the fourth lines. The synapses receive a first plurality of inputs as electrical voltages on gates of the transistors, and provide a first plurality of outputs as electrical currents on the third lines.