公开(公告)号：US11947476B2

公开(公告)日：2024-04-02

申请号：US17710413

申请日：2022-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Bryan Broussard ,  Pravesh Gupta ,  Benjamin Tsien ,  Vydhyanathan Kalyanasundharam

IPC: G06F13/20

CPC classification number: G06F13/20 ,  G06F2213/40

Abstract: Methods and systems are disclosed for cross-chiplet performance data streaming. Techniques disclosed include accumulating, by a subservient chiplet, event data associated with an event indicative of a performance aspect of the subservient chiplet; sending, by the subservient chiplet, the event data over a chiplet bus to a master chiplet; and adding, by the master chiplet, the received event data to an event record, the event record containing previously received, from the subservient chiplet over the chiplet bus, event data associated with the event.

公开(公告)号：US11947473B2

公开(公告)日：2024-04-02

申请号：US17499494

申请日：2021-10-12

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Haikun Dong ,  Kostantinos Danny Christidis ,  Ling-Ling Wang ,  MinHua Wu ,  Gaojian Cong ,  Rui Wang

IPC: G06F13/16 ,  G06F3/06

CPC classification number: G06F13/1673 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0688

Abstract: Systems, apparatuses, and methods for implementing duplicated registers for access by initiators across multiple semiconductor dies are disclosed. A system includes multiple initiators on multiple semiconductor dies of a chiplet processor. One of the semiconductor dies is the master die, and this master die has copies of registers which can be accessed by the multiple initiators on the multiple semiconductor dies. When a given initiator on a given secondary die generates a register access, the register access is routed to the master die and a particular duplicate copy of the register maintained for the given secondary die. From the point of view of software, the multiple semiconductor dies appear as a single die, and the multiple initiators appear as a single initiator. Multiple types of registers can be maintained by the master die, with a flush register being one of the register types.

公开(公告)号：US11947380B2

公开(公告)日：2024-04-02

申请号：US17890520

申请日：2022-08-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ranjith Kumar Sajja ,  Sreekanth Godey ,  Anirudh R. Acharya

IPC: G06F1/08 ,  G06F1/12 ,  G06F9/50 ,  G06F11/34

CPC classification number: G06F1/08 ,  G06F1/12 ,  G06F9/505 ,  G06F11/3409

Abstract: Systems and methods related to controlling clock signals for clocking shader engines modules (SEs) and non-shader-engine modules (nSEs) of a graphics processing unit (GPU) are provided. One or more dividers receive a clock signal CLK and output a clock signal CLKA to the SEs and output a clock signal CLKB to the nSEs. The frequencies of CLKA and CLKB are independently selected based on sets of performance counter data monitored at the SEs and nSEs, respectively. The clock signal frequency for either the SEs or the nSEs is reduced when the corresponding sets of performance counter data indicates a comparatively lower processing workload for the SEs or for the nSEs.

公开(公告)号：US20240104844A1

公开(公告)日：2024-03-28

申请号：US17955490

申请日：2022-09-28

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Sho Ikeda ,  Paritosh Vijay Kulkarni ,  Takahiro Harada

IPC: G06T17/10 ,  G06T15/06 ,  G06T17/00

CPC classification number: G06T17/10 ,  G06T15/06 ,  G06T17/005 ,  G06T2210/12 ,  G06T2210/21

Abstract: Devices and methods for multi-resolution geometric representation for ray tracing are described which include casting a ray in a space comprising objects represented by geometric shapes and approximating a volume of the geometric shapes using an accelerated hierarchy structure. The accelerated hierarchy structure comprises first nodes each representing a volume of one of the geometric shapes in the space and second nodes each representing an approximate volume of a group of the geometric shapes. When the ray is determined to intersect a bounding box of a second node representing one group of the geometric shapes, a selection is made between traversal and non-traversal of other second nodes based on a LOD for representing the volume of the one group of geometric shapes.

公开(公告)号：US20240104685A1

公开(公告)日：2024-03-28

申请号：US17955499

申请日：2022-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Ruijin Wu ,  Michael John Livesley ,  Kiia Kallio ,  Jan H. Achrenius ,  Mika Tuomi

IPC: G06T1/20 ,  G06T15/00 ,  G06T17/10

CPC classification number: G06T1/20 ,  G06T15/00 ,  G06T17/10

Abstract: Devices and methods method of tiled rendering are provided which comprises dividing a frame to be rendered, into a plurality of tiles, receiving commands to execute a plurality of subpasses of the tiles, interleaving execution of same subpasses of multiple tiles of the frame by executing one or more subpasses as skip operations, storing visibility data, for subsequently ordered subpasses of the tiles, at memory addresses allocated for data of corresponding adjacent tiles in a first direction of traversal and rendering the tiles for the subsequently ordered subpasses using the visibility data stored at the memory addresses allocated for corresponding adjacent tiles in a second direction of traversal, opposite the first direction of traversal.

公开(公告)号：US20240103763A1

公开(公告)日：2024-03-28

申请号：US17953723

申请日：2022-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Mahzabeen Islam ,  Shaizeen Dilawarhusen Aga ,  Johnathan Robert Alsop ,  MOHAMED ASSEM ABD ELMOHSEN IBRAHIM ,  Nuwan S Jayasena

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0673

Abstract: In accordance with the described techniques for bank-level parallelism for processing in memory, a plurality of commands are received for execution by a processing in memory component embedded in a memory. The memory includes a first bank and a second bank. The plurality of commands include a first stream of commands which cause the processing in memory component to perform operations that access the first bank and a second stream of commands which cause the processing in memory component to perform operations that access the second bank. A next row of the first bank that is to be accessed by the processing in memory component is identified. Further, a precharge command is scheduled to close a first row of the first bank and an activate command is scheduled to open the next row of the first bank in parallel with execution of the second stream of commands.

公开(公告)号：US20240100422A1

公开(公告)日：2024-03-28

申请号：US17955266

申请日：2022-09-28

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Yinan Jiang ,  HaiJun Chang ,  GuoQing Zhang

IPC: A63F13/335 ,  A63F13/352 ,  A63F13/358

CPC classification number: A63F13/335 ,  A63F13/352 ,  A63F13/358

Abstract: Resource use orchestration for multiple application instances is described. In accordance with the described techniques, a time interval for accessing a resource is divided into multiple time slots. In one or more implementations, the resource is a graphics processing unit. Each of a plurality of containers associated with an application is assigned to one of the multiple time slots according to a disbursement algorithm. A respective signal offset is provided to each container based on an assigned time slot of the container. The provided signal offsets cause the plurality of containers to access the resource for the application in a predetermined order.

公开(公告)号：US11942953B2

公开(公告)日：2024-03-26

申请号：US17557590

申请日：2021-12-21

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Kaushik Mazumdar ,  Joyce Cheuk Wai Wong ,  Naeem Ibrahim Ally ,  Stephen Victor Kosonocky

IPC: H03L7/08 ,  H03L7/085

CPC classification number: H03L7/0805 ,  H03L7/085

Abstract: A apparatus includes a reference signal generator, a droop detection circuit, a digital frequency-locked loop (DFLL), and a DFLL control circuit. The reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value. The droop detection circuit converts the pulse-density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop of the monitored supply voltage below a designated value relative to the analog signal, produces a droop detection signal. The DFLL provides a clock signal for synchronizing circuitry within a domain of the monitored supply voltage. The DFLL control circuit, responsive to receiving the droop detection signal, causes the DFLL to slow the clock signal.

公开(公告)号：US20240095404A1

公开(公告)日：2024-03-21

申请号：US17945750

申请日：2022-09-15

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Shaofeng An ,  Shiqi Sun ,  Michael James Tresidder ,  YanFeng Wang ,  Peter Malcolm Barnes

IPC: G06F21/64 ,  G06F16/23

CPC classification number: G06F21/64 ,  G06F16/2365

Abstract: Data integrity checks for reducing communication latency is described. A transmitting endpoint transmits data to a receiving endpoint by generating an integrity tag for a first subset of data blocks and a second integrity tag for a second subset of data blocks. In implementations, the first and second integrity tags overlap at least one data block and are offset based on computational complexities of generating the integrity tags. A receiving endpoint generates comparison tags for each of the integrity tags and uses the comparison tags to validate an authenticity of received data. In response to validating the first and second integrity tags, data blocks covered by both the first and second integrity tags are released for use. Additional integrity tags are generated and validated for subsequent subsets of data blocks during data communication, thus reducing latency by offsetting times at which comparison tags are generated and validated.

公开(公告)号：US11934764B2

公开(公告)日：2024-03-19

申请号：US17362662

申请日：2021-06-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Richard Schultz ,  Wenyi Yin ,  Tanmoy Saha

IPC: G06F30/398 ,  G06F30/392 ,  H01L27/02

CPC classification number: G06F30/398 ,  G06F30/392 ,  H01L27/0207

Abstract: Manufacturing a semiconductor chip based on redefining tolerance rules to create an otherwise prohibited structure including redefining a tolerance rule to permit creation of a minimum area metal trench structure violating the tolerance rule during a routing operation; and fabricating the minimum area metal trench structure on the semiconductor substrate based on the redefined tolerance rule.