公开(公告)号：US6163495A

公开(公告)日：2000-12-19

申请号：US398735

申请日：1999-09-17

申请人： Keith A. Ford ,  Iulian C. Gradinariu ,  Bogdan I. Georgescu ,  Sean B. Mulholland ,  John J. Silver ,  Danny L. Rose

发明人： Keith A. Ford ,  Iulian C. Gradinariu ,  Bogdan I. Georgescu ,  Sean B. Mulholland ,  John J. Silver ,  Danny L. Rose

IPC分类号： G11C11/417 ,  G11C8/12 ,  G11C8/14 ,  G11C8/18 ,  G11C11/41 ,  G11C11/413 ,  G11C29/04 ,  G11C8/00

CPC分类号： G11C8/14 ,  G11C8/12 ,  G11C8/18

摘要： A circuit comprising a first and second bitline, a plurality of groups of memory cells and a control circuit. The first and second bitlines may each be configured to read and write to one or more of the plurality of groups of memory cells. Each of the plurality of bitline pairs may be interdigitated. The control circuit may be configured to select an active group of said plurality of groups in response to one or more control signals. The control circuit may be implemented within the groups of memory cells.

摘要翻译： 一种包括第一和第二位线，多组存储器单元和控制电路的电路。 第一和第二位线可以各自被配置为读取和写入多个存储器单元组中的一个或多个。 多个位线对中的每一个可以是交叉的。 控制电路可以被配置为响应于一个或多个控制信号来选择所述多个组的活动组。 控制电路可以在存储器单元组内实现。

公开(公告)号：US6163481A

公开(公告)日：2000-12-19

申请号：US431296

申请日：1999-10-29

申请人： Shigekasu Yamada ,  Colin S. Bill ,  Michael A. VanBuskirk

发明人： Shigekasu Yamada ,  Colin S. Bill ,  Michael A. VanBuskirk

IPC分类号： G11C16/06 ,  G11C8/08 ,  G11C8/14 ,  G11C16/08 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

CPC分类号： G11C16/08 ,  G11C8/08 ,  G11C8/14

摘要： A wordline tracking structure for use in an array of Flash EEPROM memory cells is provided. The tracking structure serves to match reference and sector core wordline voltages across the entire chip regardless of sector location. The tracking structure includes a second VPXG conductor line operatively connected between sector wordlines of a "far" sector and a reference cell mini-array. The second VPXG conductor line has a substantially smaller time constant than in a first VPXG conductor line operatively connected between an output of a boosting circuit and the sector wordlines of the "far" sector. As a consequence, the reference wordline voltage associated with the reference cell mini-array will track closely the sector wordline voltage during the read operation regardless of the location of the selected sector.

摘要翻译： 提供了一种用于闪存EEPROM存储单元阵列的字线跟踪结构。 跟踪结构用于匹配整个芯片上的参考和扇区核心字线电压，而不考虑扇区位置。 跟踪结构包括可操作地连接在“远”扇区的扇区字线与参考单元微阵列之间的第二VPXG导体线。 第二VPXG导体线具有比可操作地连接在升压电路的输出和“远”部分的扇区字线之间的第一VPXG导线中的时间常数更小的时间常数。 因此，与参考单元小型阵列相关联的参考字线电压将在读取操作期间密切跟踪扇区字线电压，而与所选扇区的位置无关。

公开(公告)号：US6160753A

公开(公告)日：2000-12-12

申请号：US504781

申请日：2000-02-15

申请人： Akinori Shibayama

发明人： Akinori Shibayama

IPC分类号： G11C11/41 ,  G11C8/14 ,  G11C11/401 ,  G11C11/407 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  G11C8/08

CPC分类号： G11C8/14

摘要： Each sub-word line drive circuit SWD in a sub-word line drive section SWLB receives a signal carried by a main word line MWL0, a sub-word line non-selection signal XWD, and a sub-word line drive signal WD to drive a sub-word line SW. The sub-word line non-selection signal XWD is generated by an inverter XWDG in an intersection region SDR based on the sub-word line drive signal WD received by the inverter. The active level of the sub-word line drive signal WD is an internal boosted potential VPP which is higher than the external supply potential VDD. By using as the inactive level of the sub-word line non-selection signal XWD an internal lowered potential VINT which is lower than the external supply potential VDD, power consumption of an internal boosted potential generation circuit is reduced.

摘要翻译： 子字线驱动部分SWLB中的每个子字线驱动电路SWD接收由主字线MWL0，子字线非选择信号XWD和子字线驱动信号WD所携带的信号以驱动 子字线SW。 子字线非选择信号XWD由交流区域SDR中的反相器XWDG基于由逆变器接收的子字线驱动信号WD产生。 子字线驱动信号WD的有效电平是比外部电源电位VDD高的内部升压电位VPP。 通过将子字线非选择信号XWD的无效电平用作低于外部电源VDD的内部降低电位VINT，内部升压电位产生电路的功耗降低。

公开(公告)号：US6084818A

公开(公告)日：2000-07-04

申请号：US283247

申请日：1999-04-01

申请人： Tsukasa Ooishi

发明人： Tsukasa Ooishi

IPC分类号： G11C11/407 ,  G11C8/14 ,  G11C11/401 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4096 ,  G11C11/4097 ,  G11C29/00 ,  G11C29/04 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C29/848 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4096 ,  G11C11/4097 ,  G11C8/14

摘要： Four subordinate word lines are driven for a single main word line. In a subordinate word driver circuit, a bank select line activated allows a potential level of a main word line to be transmitted to an internal node via a first transistor. Simultaneously, a select line is also active and a potential level of the internal node is transmitted to a subordinate word line via a second transistor. A bank select line is inactivated and the select line is then further boosted to a boosted potential so that it is driven to a boosted potential of a potential level of the subordinate word line.

公开(公告)号：US6069838A

公开(公告)日：2000-05-30

申请号：US280065

申请日：1999-03-29

申请人： Jae-Hong Jeong

发明人： Jae-Hong Jeong

IPC分类号： G11C11/407 ,  G11C8/08 ,  G11C8/14 ,  G11C8/00

CPC分类号： G11C8/08 ,  G11C8/14

摘要： A semiconductor memory device having a sub-word line driving circuit overcoming disadvantages of a conventional semiconductor memory device having a sub-word line driving circuit in that it requires additional NMOS transistors with their gates applied with a predecoding signal in order to connect all sub-word lines to the ground which may be floated during the operation of the sub-word line driving circuit, and thus a layout of the device is complicated and a size of the memory chip is increased, can simplify the device layout and reduce the memory chip size by using the NMOS transistor connecting the adjacent sub-word lines which are applied with an identical predecoding signal but receive different inverted global word line enable signals.

摘要翻译： 一种具有子字线驱动电路的半导体存储器件，其克服了具有子字线驱动电路的常规半导体存储器件的缺点，因为它需要额外的NMOS晶体管，其门施加预解码信号，以便连接所有子字线驱动电路， 在子字线驱动电路的操作期间可能浮动的地线的字线，因此器件的布局复杂，并且存储器芯片的尺寸增加，可以简化器件布局并减少存储器芯片 通过使用连接相邻子字线的NMOS晶体管，其被施加相同的预解码信号，但是接收不同的反向全局字线使能信号。

公开(公告)号：US6069815A

公开(公告)日：2000-05-30

申请号：US993538

申请日：1997-12-18

申请人： Gerhard Mueller ,  Toshiaki Kirihata ,  Hing Wong

发明人： Gerhard Mueller ,  Toshiaki Kirihata ,  Hing Wong

IPC分类号： G11C11/401 ,  G11C7/18 ,  G11C8/14 ,  G11C16/06 ,  G11C5/06

CPC分类号： G11C7/18 ,  G11C8/14

摘要： Disclosed is a semiconductor memory having a hierarchical bit line and/or word line architecture. In one embodiment, a memory having a hierarchical bit line architecture, particularly suitable for cells smaller than 8F.sup.2, includes a master bit line pair in each column, including first and second master bit lines with portions vertically spaced from one another. The first and second master bit lines twist with respect to one another in the vertical direction such that the first master bit line alternately overlies and underlies the second master bit line. A plurality of local bit line pairs in each column are coupled to memory cells, with at least one of the local bit lines coupled to a master bit line. In other embodiments, hierarchical word line configurations are disclosed including master word lines, sub-master word lines, and local word lines, electrically interconnected to one another via either switches, electrical contacts, or electrical circuits.

摘要翻译： 公开了具有分级位线和/或字线架构的半导体存储器。 在一个实施例中，具有特别适合于小于8F2的小区的分层位线架构的存储器包括每列中的主位线对，包括彼此垂直间隔开的部分的第一和第二主位线。 第一和第二主位线在垂直方向上相对于彼此扭曲，使得第一主位线交替地覆盖并位于第二主位线下方。 每列中的多个局部位线对耦合到存储器单元，其中至少一个局部位线耦合到主位线。 在其他实施例中，公开了分层字线配置，包括主字线，子主字线和本地字线，经由开关，电触点或电路彼此电互连。

公开(公告)号：US6054918A

公开(公告)日：2000-04-25

申请号：US938077

申请日：1997-09-26

申请人： John Christian Holst

发明人： John Christian Holst

IPC分类号： G06F7/02 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/14 ,  G11C11/418 ,  G11C15/04 ,  G11C29/02 ,  G11C29/32 ,  G11C29/50 ,  H03K3/356 ,  H03K5/00 ,  H03K5/13 ,  H03L7/08 ,  H03L7/099

CPC分类号： G11C15/04 ,  G06F12/0895 ,  G06F7/02 ,  G11C11/418 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/026 ,  G11C29/028 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/22 ,  G11C8/14 ,  H03K3/356156 ,  H03K5/13 ,  H03L7/08 ,  G11C11/401 ,  G11C11/41 ,  G11C16/04 ,  G11C17/14 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/0995 ,  Y02B60/1225

摘要： A multiple-bit comparator achieves a fast operating speed and accurate operation through the connection of multiple individual-bit comparison devices to a first line and the connection of a timing device to a second line. The first line and the second line are differentially sensed to generate a signal designating whether all bits match or not. In some embodiments, the replica timing device is timed using a timing signal replicating the application of data to the individual-bit comparison devices and generates a signal on the second line that is delayed in comparison to the multiple-bit comparison signal on the first line by reduced sizing of the timing device in comparison to the individual-bit comparison devices. In some embodiments, a differential comparator includes a sense amplifier that is self-timed rather than utilizing a strobe signal to supply timing. In some embodiments, the sense amplifier includes a cross-coupled device that sources current between differential sides of the sense amplifier. A typical cross-coupled device supports a bias current, consuming power when the circuit is inactive. However, the present sense amplifier includes a precharge switch that stops current drain in the sense amplifier when the amplifier is inactive.

摘要翻译： 多比特比较器通过将多个单独比特比较装置连接到第一条线路并将定时装置连接到第二条线路，实现了快速的操作速度和精确的操作。 差分地感测第一行和第二行以产生指定所有位是​​否匹配的信号。 在一些实施例中，复制定时装置使用将数据应用复制到各位比较装置的定时信号进行定时，并且在与第一行上的多比特比较信号相比较的第二行上产生延迟的信号 通过与各位比较装置相比减小定时装置的尺寸。 在一些实施例中，差分比较器包括自定时的读出放大器，而不是利用选通信号来提供定时。 在一些实施例中，读出放大器包括在感测放大器的差分侧之间产生电流的交叉耦合器件。 典型的交叉耦合器件支持偏置电流，当电路无效时消耗功率。 然而，本发明的读出放大器包括预放电开关，当放大器不活动时，该充电开关在读出放大器中停止电流消耗。

公开(公告)号：US6031784A

公开(公告)日：2000-02-29

申请号：US148817

申请日：1998-09-04

申请人： Adrian E. Ong

发明人： Adrian E. Ong

IPC分类号： G11C7/18 ,  G11C8/14 ,  G11C7/00

CPC分类号： G11C7/18 ,  G11C8/14

摘要： In one aspect of the invention, a circuit for the hierarchical decoding of a memory device includes a local word line for accessing a memory cell. A local word line driver, which drives the local word line, has at most two transistors, each of these transistors coupled to the local word line. In another aspect of the invention, a circuit for the hierarchical decoding of a memory device includes a local word line driver for driving a local word line. A local phase line driver is connected to the local word line driver by a single metal line. The local phase line driver cooperates with the local word line driver for accessing a memory cell.

摘要翻译： 在本发明的一个方面，用于存储器件的分层解码的电路包括用于访问存储器单元的本地字线。 驱动本地字线的本地字线驱动器具有至多两个晶体管，这些晶体管中的每一个耦合到本地字线。 在本发明的另一方面，用于存储器件的分层解码的电路包括用于驱动本地字线的本地字线驱动器。 局部相线驱动器通过单个金属线连接到本地字线驱动器。 本地相线驱动器与本地字线驱动器协作以访问存储单元。

公开(公告)号：US6023441A

公开(公告)日：2000-02-08

申请号：US726134

申请日：1996-10-04

申请人： Bart McDaniel

发明人： Bart McDaniel

IPC分类号： G11C8/00 ,  G11C8/14

CPC分类号： G11C8/14 ,  G11C8/00

摘要： A method and apparatus for selectively enabling individual sets of registers in a row of a register array. One embodiment of the present invention is a register array that has a number of registers arranged in a number of rows and columns. Each row of registers includes N sets of registers, where N is an integer greater than 1. The register array also includes a said selector and N said-selecting enable lines for each row of registers. Each enable line of the N set-selecting enable lines couple the set selector to one set of registers of the N sets of registers in each row. In other words, the set selector enables a particular set of registers (i.e., causes a particular set of registers to output their contents on their output bit lines) by providing an enable signal to the particular set of registers on the enable line that couples the set selector to the particular set of registers.

摘要翻译： 一种用于选择性地使得寄存器阵列的行中的寄存器的各组的方法和装置。 本发明的一个实施例是一种寄存器阵列，其具有以多个行和列排列的多个寄存器。 每行寄存器包括N组寄存器，其中N是大于1的整数。寄存器阵列还包括用于每行寄存器的所述选择器和N个所述选择使能线。 N个置位选择使能线的每个使能线将组选择器耦合到每行中的N组寄存器的一组寄存器。 换句话说，设置选择器使能一组特定的寄存器（即，使特定寄存器组在其输出位线上输出其内容），通过向使能线上的特定寄存器组提供使能信号， 将选择器设置为特定的寄存器组。

公开(公告)号：US5986966A

公开(公告)日：1999-11-16

申请号：US55956

申请日：1998-04-07

申请人： Kyoichi Nagata

发明人： Kyoichi Nagata

IPC分类号： G11C11/407 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/408 ,  G11C7/00

CPC分类号： G11C8/14 ,  G11C11/408 ,  G11C11/4085 ,  G11C8/08

摘要： In a semiconductor memory device, a plurality of main word lines a plurality of pairs of first and second sub word lines, a plurality of first sub word line drive circuits and a plurality of second sub word line drive circuits are provided. Each of the first word line drive circuits is connected to one of the main word lines and at least two pairs of the pairs of first and second sub word lines for activating and deactivating one of the first sub word lines and deactivating the second sub word lines. Each of the second sub word line drive circuits is connected to one of the main word lines and at least two pairs of the pairs of first and second sub word lines for activating and deactivating one of the second sub word lines and deactivating the first sun word lines.

摘要翻译： 在半导体存储器件中，提供多个主字线，多对第一和第二子字线，多个第一子字线驱动电路和多个第二子字线驱动电路。 第一字线驱动电路中的每一个连接到主字线之一和至少两对第一和第二子字线对，用于激活和去激活第一子字线中的一个并且去激活第二子字线 。 第二子字线驱动电路中的每一个连接到一个主字线和至少两对第一和第二子字线对，用于激活和去激活第二子字线中的一个并且去激活第一太阳字 线条。