公开(公告)号：US11749671B2

公开(公告)日：2023-09-05

申请号：US17067033

申请日：2020-10-09

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Kaustubh Shanbhag ,  Glenn Workman

IPC: H01L27/02 ,  H01L21/8238 ,  H01L21/762

CPC classification number: H01L27/0207 ,  H01L21/7624 ,  H01L21/823892

Abstract: The disclosure provides integrated circuit (IC) structures and methods to form the same. Methods according to the disclosure may be performed on a substrate having a first doping type, the substrate extending between a first end and a second end. A deep well is formed within the substrate, the deep well including a well boundary defined between the deep well and a remainder of the substrate. The well boundary is horizontally distal to a midpoint between the first end and the second end of the substrate. A first active semiconductor region is formed at least partially over the substrate, and an oppositely-doped second active semiconductor region is formed at least partially over the deep well.

公开(公告)号：US11749559B2

公开(公告)日：2023-09-05

申请号：US17983436

申请日：2022-11-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Siva P. Adusumilli

IPC: H01L21/763 ,  H01L29/06 ,  H01L27/12 ,  H01L21/762 ,  H01L21/324 ,  H01L21/84 ,  H01L21/265 ,  H01L21/74 ,  H01L29/32 ,  H01L21/02 ,  H01L27/06 ,  H01L29/10

CPC classification number: H01L21/763 ,  H01L21/26506 ,  H01L21/26526 ,  H01L21/26533 ,  H01L21/324 ,  H01L21/743 ,  H01L21/76267 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/32 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L27/0629 ,  H01L29/1087

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

公开(公告)号：US11747560B2

公开(公告)日：2023-09-05

申请号：US17411122

申请日：2021-08-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Roderick A. Augur

IPC: G02B6/122 ,  G02B6/125 ,  G02B6/12 ,  G02B6/136

CPC classification number: G02B6/1228 ,  G02B6/125 ,  G02B6/136 ,  G02B2006/12061

Abstract: Disclosed is a photonic integrated circuit (PIC) structure including: a first waveguide with a first main body and a first end portion, which is tapered; and a second waveguide with a second main body and a second end portion, which has two branch waveguides that are positioned adjacent to opposing sides, respectively, of the first end portion of the first waveguide and that branch out from the second main body, thereby forming a V, U or similar shape. The arrangement of the two branch waveguides of the second end portion of the second waveguide relative to the tapered first end portion of the first waveguide allows for mode matching conditions to be met at multiple locations at the interface between the waveguides, thereby creating multiple signal paths between the waveguides and effectively reducing the light signal power density along any one path to prevent or at least minimize any power-induced damage.

公开(公告)号：US20230273369A1

公开(公告)日：2023-08-31

申请号：US17680421

申请日：2022-02-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Yusheng Bian ,  Steven M. Shank ,  Judson Holt

IPC: G02B6/122 ,  H01L21/84 ,  G02B6/136

CPC classification number: G02B6/122 ,  G02B6/136 ,  H01L21/84

Abstract: Photonics structures including an optical component and methods of fabricating a photonics structure including an optical component. The photonics structure includes an optical component, a substrate having a cavity and a dielectric material in the cavity, and a dielectric layer positioned in a vertical direction between the optical component and the cavity. The optical component is positioned in a lateral direction to overlap with the cavity in the substrate.

公开(公告)号：US11744166B2

公开(公告)日：2023-08-29

申请号：US17007759

申请日：2020-08-31

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Lanxiang Wang ,  Shyue Seng Tan ,  Eng Huat Toh

IPC: H01L45/00 ,  H10N70/00 ,  H10B63/00

CPC classification number: H10N70/841 ,  H10B63/00 ,  H10N70/063 ,  H10N70/8833

Abstract: Structures for a resistive memory element and methods of forming a structure for a resistive memory element. The resistive memory element has a first electrode, a second electrode, a third electrode, and a switching layer. The first electrode is coupled to the switching layer, the second electrode is coupled to a side surface of the switching layer, and the third electrode is coupled to the switching layer.

公开(公告)号：US11742283B2

公开(公告)日：2023-08-29

申请号：US17139117

申请日：2020-12-31

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Kah Wee Gan ,  Benfu Lin ,  Yun Ling Tan

IPC: H01L23/522 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H01L49/02

CPC classification number: H01L23/5228 ,  H01L28/20 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an integrated thin film resistor with a memory device and methods of manufacture. The structure includes a memory device in back end of line (BEOL) materials and a thin film resistor located in the BEOL materials. The thin film resistor includes electrical resistive material, and an insulator material over the electrical resistive material is thicker than insulator material over the memory device.

公开(公告)号：US20230268401A1

公开(公告)日：2023-08-24

申请号：US17747476

申请日：2022-05-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hong Yu ,  Jianwei Peng ,  Vibhor Jain

IPC: H01L29/417 ,  H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/41708 ,  H01L29/7371 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/42304 ,  H01L29/66242

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with self-aligned asymmetric spacer and methods of manufacture. The structure includes: a base formed on a semiconductor substrate; an asymmetrical spacer surrounding the base; an emitter on a first side of the base and separated from the base by the asymmetrical spacer; and a collector on a second side of the base and separated from the base by the asymmetrical spacer.

公开(公告)号：US20230267259A1

公开(公告)日：2023-08-24

申请号：US17679178

申请日：2022-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Navneet Jain ,  Mahbub Rashed

IPC: G06F30/392 ,  G06F30/398

CPC classification number: G06F30/392 ,  G06F30/398 ,  G06F2111/20

Abstract: Disclosed are embodiments of a computer-aided design system and corresponding method for power-optimized timing closure of an integrated circuit (IC) design. In the embodiments, a cell library includes sets of cells, where each cell in the same set has the same internal structure but different combinations of cell boundary isolation structures associated with different passive delay values. Timing closure includes replacement of a cell in a previously generated layout with another cell from the same set in order to adjust delay (e.g., increase delay) of a data signal or clock signal and, thereby facilitate fixing of a previously identified violation of a timing constraint. By eliminating or at least minimizing the need to insert buffer and/or inverter cells into a layout to add delay to a data signal and/or a clock signal during timing closure, the embodiments avoid or at least limit concurrent increases in power consumption and area consumption.

公开(公告)号：US20230266526A1

公开(公告)日：2023-08-24

申请号：US17674905

申请日：2022-02-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Yusheng Bian ,  Francis O. Afzal

IPC: G02B6/028 ,  G02B6/036

CPC classification number: G02B6/0288 ,  G02B6/036

Abstract: Disclosed is an optical waveguide including a waveguide core and waveguide cladding surrounding the waveguide core. The waveguide cladding includes at least one stack of cladding material layers positioned laterally adjacent to a sidewall of the waveguide core such that each cladding material layer in the stack abuts the sidewall of the waveguide core. Each of the cladding material layers in the stack has a smaller refractive index than the waveguide core and at least two of the cladding material layers in the stack have different refractive indices, thereby tailoring field confinement and reshaping the optical mode. Different embodiments include different numbers of cladding material layers in the stack, different stacking orders of the cladding material layers, different waveguide core types, symmetric or asymmetric cladding structures on opposite sides of the waveguide core, etc. Also disclosed is a method of forming the optical waveguide.

公开(公告)号：US11728381B2

公开(公告)日：2023-08-15

申请号：US17238755

申请日：2021-04-23

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Kyongjin Hwang ,  Raunak Kumar ,  Robert J. Gauthier, Jr.

IPC: H01L29/10 ,  H01L29/66 ,  H01L27/02 ,  H01L29/735

CPC classification number: H01L29/1008 ,  H01L27/0259 ,  H01L27/0288 ,  H01L29/6625 ,  H01L29/735

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure includes a bipolar transistor device, including a base region, having a base contact region, in a first well of a first conductivity type, a collector region, having a collector contact region, in a second well of a second conductivity type, and an emitter region, having an emitter contact region, in the first well, located between the base contact region and the second well, and a reverse-doped resistance well, of the second conductivity type, located in the first well of the first conductivity type between the base contact region and the emitter contact region structured to decrease turn-on voltage of the bipolar transistor device.