公开(公告)号：US08591264B2

公开(公告)日：2013-11-26

申请号：US13751865

申请日：2013-01-28

Applicant: MOSAID Technologies Incorporated

Inventor： Yehuda Binder

IPC: H01R25/00

CPC classification number: H01R31/005 ,  H01R31/065 ,  H04B3/542 ,  H04B2203/5425 ,  H04B2203/5437 ,  H04B2203/5441 ,  H04B2203/5445 ,  H04B2203/545 ,  H04B2203/5454 ,  H04B2203/5491 ,  H04B2203/5495 ,  H04L12/2856 ,  H04L12/2898 ,  H04N7/102 ,  H04N7/106 ,  H04Q11/04 ,  H04Q2213/13012 ,  H04Q2213/1308 ,  H04Q2213/13196 ,  H04Q2213/13199 ,  H04Q2213/13332 ,  H04Q2213/13389

Abstract: In conjunction with a wiring in a house carrying data network signal, a modular outlet (100) includes a base module (100a) and interface module (100b). The base module connects to the wiring and is attached to the surface of a building. The interface module provides a data unit connection. The interface module is mechanically attached to the base module and electrically connected thereto. The wiring may also carry basic service signal such as telephone, electrical power and cable television (CATV). In such a case, the outlet provides the relevant connectivity either as part of the base module or as part of the interface module. Both proprietary and industry standard interfaces can be used to interconnect the module. Furthermore, a standard computer expansion card (such as PCI, PCMCIA and alike) may be used as interface module.

公开(公告)号：US20130249592A1

公开(公告)日：2013-09-26

申请号：US13903319

申请日：2013-05-28

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Peter B. GILLINGHAM

IPC: H03K3/012 ,  H03K19/00

CPC classification number: H03K3/012 ,  H01L2924/0002 ,  H03K19/0005 ,  H03K19/00361 ,  H04L25/0278 ,  H01L2924/00

Abstract: In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage.

Abstract translation: 在具有连接到内部部分的端子的半导体器件中，用于为器件的端子提供管芯端接的终端电路。 终端电路包括多个晶体管，其包括连接在端子和电源之间的至少一个NMOS晶体管和至少一个PMOS晶体管; 以及控制电路，用于以相应的NMOS栅极电压驱动每个NMOS晶体管的栅极并且用相应的PMOS栅极电压驱动每个PMOS晶体管的栅极，所述控制电路被配置为控制NMOS和PMOS栅极电压，以便 当使能片上端接时，将晶体管置于欧姆区域。 电源提供小于每个所述NMOS栅极电压并大于每个所述PMOS栅极电压的电压。

公开(公告)号：US20130242653A1

公开(公告)日：2013-09-19

申请号：US13892743

申请日：2013-05-13

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Jin-Ki KIM

IPC: G11C16/34

CPC classification number: G11C16/34 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/344 ,  G11C16/3454 ,  G11C2211/5621

Abstract: A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages.

公开(公告)号：US20130229874A1

公开(公告)日：2013-09-05

申请号：US13867437

申请日：2013-04-22

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： HakJune OH ,  Hong Beom PYEON ,  Jin-Ki KIM

IPC: G11C16/10

CPC classification number: G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

公开(公告)号：US20130212304A1

公开(公告)日：2013-08-15

申请号：US13726320

申请日：2012-12-24

Applicant: MOSAID Technologies Incorporated

Inventor： Hong Beom Pyeon

IPC: G06F12/06

CPC classification number: G06F12/0669 ,  G06F13/4247

Abstract: A technique for automatically establishing device IDs for devices in a daisy chain cascade arrangement. For each device, a write ID operation is initiated at the device to cause the device to enter a generate/write ID mode. While in this mode, a first value is input to the device. The device generates a second value from the first value. The device outputs the generated second value from the device to a next device in the daisy chain cascade which uses the second value as a first value for the next device. The device then establishes its ID from the first value. The process is repeated for all devices in the daisy chain cascade arrangement.

Abstract translation: 一种用于以菊花链级联布置自动建立设备的设备ID的技术。 对于每个设备，在设备上启动写入ID操作，以使设备进入生成/写入ID模式。 在此模式下，第一个值被输入到设备。 设备从第一个值生成第二个值。 设备将生成的第二值从设备输出到菊花链级联中的下一个设备，其使用第二个值作为下一个设备的第一个值。 然后设备从第一个值建立其ID。 对菊花链级联布置中的所有设备重复该过程。

公开(公告)号：US20130210283A1

公开(公告)日：2013-08-15

申请号：US13751865

申请日：2013-01-28

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Yehuda BINDER

IPC: H01R31/06

CPC classification number: H01R31/005 ,  H01R31/065 ,  H04B3/542 ,  H04B2203/5425 ,  H04B2203/5437 ,  H04B2203/5441 ,  H04B2203/5445 ,  H04B2203/545 ,  H04B2203/5454 ,  H04B2203/5491 ,  H04B2203/5495 ,  H04L12/2856 ,  H04L12/2898 ,  H04N7/102 ,  H04N7/106 ,  H04Q11/04 ,  H04Q2213/13012 ,  H04Q2213/1308 ,  H04Q2213/13196 ,  H04Q2213/13199 ,  H04Q2213/13332 ,  H04Q2213/13389

Abstract: In conjunction with a wiring in a house carrying data network signal, a modular outlet (100) includes abuse module (100a) and interface module (100b). The base module connects to the wiring and is attached to the surface of a building. The interface module provides a data unit connection. The interface module is mechanically attached to the base module and electrically connected thereto. The wiring may also carry basic service signal such as telephone, electrical power and cable television (CAIN). In such a case, the outlet provides the relevant connectivity either as part of the base module or as part of the interface module. Both proprietary and industry standard interfaces can be used to interconnect the module. Furthermore, a standard computer expansion card (such as PCI, PCMCIA and alike) may be used as interface module.

Abstract translation: 结合携带数据网络信号的房屋中的布线，模块化插座（100）包括滥用模块（100a）和接口模块（100b）。 基座模块连接到布线并连接到建筑物的表面。 接口模块提供数据单元连接。 接口模块机械连接到基座模块并与其电连接。 接线还可以携带基本的服务信号，如电话，电力和有线电视（CAIN）。 在这种情况下，插座提供相关连接，作为基本模块的一部分或作为接口模块的一部分。 专有和行业标准接口均可用于互连模块。 此外，可以使用标准计算机扩展卡（例如PCI，PCMCIA等）作为接口模块。

公开(公告)号：US20130208596A1

公开(公告)日：2013-08-15

申请号：US13795070

申请日：2013-03-12

Applicant: Mosaid Technologies Incorporated

Inventor： David BROWN

IPC: H04L12/26

CPC classification number: H04L45/54 ,  G06F17/30949 ,  H04L47/21 ,  H04L49/205 ,  H04L49/3009 ,  H04L49/351

Abstract: Management of congestion level, in a computer-related context, is disclosed. Also disclosed is a system generating a plurality of computer network-related tables during system operation. A number of the tables are each separately indexed by a different index. The system includes at least one tangible computer-readable medium adapted to store, at each indexed location, a swap count providing an indication of the congestion level of the indexed location. The system also includes insert logic stored as instructions on the at least one medium for execution. When executed, the insert logic is operable to: i) insert, when a predetermined condition has been satisfied, a new entry by overwriting the current entry stored in the indexed location having the lowest swap count; and ii) update the swap counts in each of the indexed locations in a manner that maintains the total swap count at least substantially constant over time.

Abstract translation: 在计算机相关的背景下披露拥塞程度的管理。 还公开了在系统操作期间生成多个计算机网络相关表的系统。 多个表分别由不同的索引分别索引。 该系统包括至少一个有形的计算机可读介质，其适于在每个索引的位置处存储提供索引位置的拥塞级别的指示的交换计数。 该系统还包括存储为用于执行的至少一个介质上的指令的插入逻辑。 当执行时，插入逻辑可操作为：i）当已经满足预定条件时，通过重写存储在具有最低交换次数的索引位置中的当前条目来插入新条目; 以及ii）以保持总交换计数至少基本上恒定的方式来更新每个索引位置中的交换计数。

公开(公告)号：US20130201775A1

公开(公告)日：2013-08-08

申请号：US13836702

申请日：2013-03-15

Applicant: MOSAID Technologies Incorporated

Inventor： Roland Schuetz ,  Jin-Ki Kim

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093

Abstract: An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.

公开(公告)号：US20130170294A1

公开(公告)日：2013-07-04

申请号：US13777485

申请日：2013-02-26

Applicant: Mosaid Technologies Incorporated

Inventor： Jin-Ki Kim ,  William F. Petrie

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/26 ,  G11C29/00 ,  G11C2211/5646 ,  G11C2211/5647

Abstract: A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively inverting data words to maximize a number of bits to be programmed within (M-1) virtual pages and selectively inverts data words to minimize a number of bits to be programmed in an Mth virtual page where M is the number of bits per cell. A corresponding polarity control flag is set when a data word is inverted. Data is selectively inverted according the corresponding polarity flag when being read from the M virtual pages. A number of the highest threshold voltage programming states in reduced. This provides tighter distribution of programmed cell threshold voltage, reduced power consumption, reduced programming time, and enhanced device reliability.

Abstract translation: 一种多位单元（MBC）非易失性存储装置，方法和系统，其中用于向/从存储器阵列写入/读取数据的控制器通过选择性地反转数据字来控制数据的极性，以使位的数量最大化 （M-1）个虚拟页面内编程，并选择性地反转数据字以最小化要在第M个虚拟页面中编程的位数，其中M是每个单元的位数。 当数据字反转时，设置相应的极性控制标志。 当从M个虚拟页面读取时，根据相应的极性标志选择性地反转数据。 许多最高阈值电压编程状态在减少。 这提供了编程单元阈值电压的更严格的分配，降低的功耗，减少的编程时间和增强的器件可靠性。

公开(公告)号：US20130163175A1

公开(公告)日：2013-06-27

申请号：US13720951

申请日：2012-12-19

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Jin-Ki KIM ,  Dae-Hee YI

IPC: G06F1/16

CPC classification number: G06F1/16 ,  G06F1/1658 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0688 ,  G11C7/1003

Abstract: A solid-state drive architecture and arrangement for standardized disk drive form factors, PCI type memory cards and general motherboard memory. The solid-state drive architecture is modular in that a main printed circuit board (PCB) of the memory system includes a host interface connector, a memory controller, and connectors. Each connector can removably receive a memory blade, where each memory blade includes a plurality of memory devices serially connected to each other via a serial interface. Each memory blade includes a physical serial interface for providing data and control signals to a first memory device in the serial chain and for receiving data and control signals from a last memory device in the serial chain. Each memory blade can be sized in length and width to accommodate any number of memory devices on either side thereof.

Abstract translation: 一种用于标准化磁盘驱动器外形尺寸的固态驱动架构和布局，PCI型存储卡和通用主板内存。 固态驱动架构是模块化的，其中存储器系统的主印刷电路板（PCB）包括主机接口连接器，存储器控制器和连接器。 每个连接器可移除地接收存储器刀片，其中每个存储器刀片包括通过串行接口彼此串行连接的多个存储器件。 每个存储器刀片包括物理串行接口，用于向串行链中的第一存储器件提供数据和控制信号，并用于从串行链中的最后一个存储器件接收数据和控制信号。 每个存储器刀片的尺寸可以在长度和宽度上以适应其任一侧上的任何数量的存储器件。