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公开(公告)号：US20230281092A1
公开(公告)日：2023-09-07
申请号：US18317420
申请日：2023-05-15
Applicant: STMicroelectronics International N.V.
Inventor： Avneep Kumar Goyal
IPC: G06F11/263 , G06F1/06 , G06F11/22
CPC classification number: G06F11/263 , G06F1/06 , G06F11/2236
Abstract: An apparatus includes a main core processor configured to receive a first signal through a first main buffer, a second signal through a second main buffer, a third signal through a third main buffer, and a fourth signal through a fourth main buffer, a shadow core processor configured to receive the first signal through a first shadow buffer, the second signal through a second shadow buffer, the third signal through a third shadow buffer and the fourth signal through a fourth shadow buffer, and a first glitch suppression buffer coupled to a common node of an input of the first main buffer and an input of the first shadow buffer.
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公开(公告)号：US20230275586A1
公开(公告)日：2023-08-31
申请号：US18098421
申请日：2023-01-18
Applicant: STMicroelectronics International N.V.
Inventor： Sandeep KAUSHIK , Paras GARG
IPC: H03K19/0185 , H03K17/687 , H03K19/017
CPC classification number: H03K19/018514 , H03K19/018585 , H03K17/6871 , H03K19/01707
Abstract: A Low Voltage Differential Signaling (LVDS) transmitter includes driver circuit with a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor. The first transistor is coupled between a first node and first output. The second transistor is coupled between the first node and a second output. The third transistor is coupled between the first output and a second node. The fourth transistor is coupled between the second output and the second node. The first resistor is coupled between the first output and a common mode node. The second resistor is coupled between the second output and the common mode node. A pre-driver circuit generates gate control signals controlling the first, second, third, and fourth transistors in response to a data signal. A controlled timing delay is applied to the timing of logic state transistors for the control signals.
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公开(公告)号：US11726514B2
公开(公告)日：2023-08-15
申请号：US17242067
申请日：2021-04-27
Applicant: STMicroelectronics International N.V.
Inventor： Shashwat , Rajesh Narwal
Abstract: An active compensation circuit for compensating the stability of a regulator is provided. The active compensation circuit presents an equivalent capacitance and an equivalent resistance and compensates stability of system using the equivalent capacitance and the equivalent resistance. The regulator includes a power transistor that receives a driving signal and channelize the required current to the Ips driven by this block. The regulator's stability is compensated using the active compensation circuit to provide an accurate output voltage without significantly compromising the accuracy (load regulation) and area of the system.
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公开(公告)号：US11713998B2
公开(公告)日：2023-08-01
申请号：US17663915
申请日：2022-05-18
Inventor： Nicolas Moeneclaey , Sri Ram Gupta , Sarika Kushwaha
CPC classification number: G01J1/4204 , G01J1/44 , G01J2001/446
Abstract: According to one aspect, an ambient-light sensor includes a photodiode configured to generate an electrical signal according to an ambient light, a capacitive-feedback transimpedance amplifier connected at its input to the photodiode for receiving a signal generated by the photodiode and for generating as an output an amplified signal from the signal generated by the photodiode, and an auto-zero switch at the input of the capacitive-feedback transimpedance amplifier. The ambient-light sensor further includes a control circuit including a bootstrap circuit configured to receive an initial positive- or zero-voltage logic control signal, and then generate, from this initial logic control signal, an adapted logic control signal having a first positive voltage level and a second negative voltage control level for controlling the auto-zero switch.
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公开(公告)号：US11710032B2
公开(公告)日：2023-07-25
申请号：US18055245
申请日：2022-11-14
Inventor： Surinder Pal Singh , Thomas Boesch , Giuseppe Desoli
CPC classification number: G06N3/063 , G06F17/18 , G06F18/217 , G06N3/04 , G06N3/08
Abstract: A convolutional neural network includes a pooling unit. The pooling unit performs pooling operations between convolution layers of the convolutional neural network. The pooling unit includes hardware blocks that promote computational and area efficiency in the convolutional neural network.
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Patent Agency Ranking
公开(公告)号：US20230231559A1
公开(公告)日：2023-07-20
申请号：US18151337
申请日：2023-01-06
Applicant: STMicroelectronics International N.V.
Inventor： Kallol CHATTERJEE , Rohit Kumar GUPTA
IPC: H03K19/0185
CPC classification number: H03K19/018521
Abstract: Provided is a voltage level shifter that operates in sub-threshold voltages. The level shifter includes a level shifting stage. The level shifting stage receives a first signal from a first voltage domain and outputs a second signal to a second voltage domain. The level shifter includes a first auxiliary stage. In response to the first signal having a first voltage level corresponding to a first logical state and a first node of the level shifting stage having a supply voltage level, the first auxiliary stage sources current to a second node of the level shifting stage. Sourcing the current to the second node accelerates a transition of the first node to a reference voltage. The level shifting stage outputs a second signal to a second voltage domain.
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公开(公告)号：US11695326B2
公开(公告)日：2023-07-04
申请号：US17058101
申请日：2019-05-14
Applicant: STMicroelectronics International N.V.
Inventor： Laurent Guillot , Thierry Sutto , Gérald Augustoni
Abstract: A half-bridge electronic device comprises, in series, a low level switch and a high level switch connected at a central point, and respectively controlled by a first and a second activation/deactivation signal. The device comprises: a first and a second synchronization system configured to interpret a variation in the voltage at the central point, respectively along a falling edge and along a rising edge, and to respectively generate a first and a second synchronization signal separate from the first; a first and a second AND type logic gate respectively combining the first synchronization signal with a first control signal and the second synchronization signal with a second control signal, in order to respectively form the first and second activation/deactivation signals.
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公开(公告)号：US20230198386A1
公开(公告)日：2023-06-22
申请号：US18168936
申请日：2023-02-14
Inventor： Vikas Rana , Marco Pasotti , Fabio De Santis
IPC: H02M3/07
Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.
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公开(公告)号：US20230186067A1
公开(公告)日：2023-06-15
申请号：US18167366
申请日：2023-02-10
Inventor： Surinder Pal SINGH , Thomas BOESCH , Giuseppe DESOLI
IPC: G06N3/063 , G06T7/62 , G06T7/11 , G06F16/901 , G06F9/38 , G06N3/08 , G06T15/08 , G06V10/82 , G06F18/22 , G06N3/045
CPC classification number: G06N3/063 , G06T7/62 , G06T7/11 , G06F16/9024 , G06F9/3877 , G06N3/08 , G06T15/08 , G06V10/82 , G06F18/22 , G06N3/045
Abstract: A device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and a communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and data volume sculpting circuitry, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting circuitry receives a series of frames, each frame formed as a two dimensional (2D) data structure, and determines a first dimension and a second dimension of each frame of the series of frames. Based on the first and second dimensions, the data volume sculpting circuitry determines for each frame a position and a size of a region-of-interest to be extracted from the respective frame, and extracts from each frame, data in the frame that is within the region-of-interest.
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公开(公告)号：US11658624B2
公开(公告)日：2023-05-23
申请号：US17461123
申请日：2021-08-30
Applicant: STMicroelectronics International N.V.
Inventor： Riju Biswas , Ratul Mitra
IPC: H03F3/45
CPC classification number: H03F3/45085 , H03F3/45475 , H03F2203/45006 , H03F2203/45026 , H03F2203/45048 , H03F2203/45084 , H03F2203/45088 , H03F2203/45211
Abstract: Disclosed herein is a method including sinking current from a pair of input transistors of a differential amplifier while sourcing more current to the pair of input transistors than is sunk. The method further includes generating a pair of input differential signals using a pair of input voltage regulators, and amplifying a difference between the pair of input differential signals to produce a pair of differential output voltages, using the differential amplifier. The method also includes amplifying the pair of differential output voltages using at least one voltage gain amplifier, and generating control signals for current sources that source the current to the pair of input transistors of the differential amplifier, from the pair of differential output voltages after at least amplification.
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