公开(公告)号：US20190102328A1

公开(公告)日：2019-04-04

申请号：US16148761

申请日：2018-10-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois TAILLIET

IPC: G06F13/16 ,  G11C16/10 ,  G11C16/34 ,  G06F3/06 ,  G06F13/42

Abstract: A value representative of a duration of the low state of a synchronization signal on a bus is measured and then compared with a threshold value. The threshold value is stored in a memory and the measured value represents, in a first comparison, a longest duration of the low states of the synchronization signal.

公开(公告)号：US10243543B2

公开(公告)日：2019-03-26

申请号：US15358245

申请日：2016-11-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Jean Nicolai ,  Albert Martinez

IPC: H03K21/00 ,  H03K3/84 ,  H03K21/02 ,  H03K23/00 ,  H03K5/06 ,  H03K19/003

Abstract: A pulse counting circuit receives pulses supplied by a source circuit having at least two inverted pulse signal supply terminals. The circuit includes a first counter to count pulses of a first pulse signal and supply a first count and a second counter to count pulses of a second pulse signal and supply a second count. A selection circuit selects one of the first and second counts.

公开(公告)号：US20190088665A1

公开(公告)日：2019-03-21

申请号：US16130593

申请日：2018-09-13

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: H01L27/11517 ,  H01L29/423 ,  H01L29/66 ,  G11C16/04 ,  G11C7/18

Abstract: An EEPROM memory integrated circuit includes memory cells arranged in a memory plane. Each memory cell includes an access transistor in series with a state transistor. Each access transistor is coupled, via its source region, to the corresponding source line and each state transistor is coupled, via its drain region, to the corresponding bit line. The floating gate of each state transistor rests on a dielectric layer having a first part with a first thickness, and a second part with a second thickness that is less than the first thickness. The second part is located on the source side of the state transistor.

公开(公告)号：US20190067309A1

公开(公告)日：2019-02-28

申请号：US16175030

申请日：2018-10-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: H01L27/11531 ,  H01L29/861 ,  G11C16/04 ,  H01L29/739 ,  H01L29/66 ,  H01L29/788 ,  H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L29/16 ,  H01L27/11526 ,  H01L27/11521 ,  H01L27/08 ,  H01L27/11536 ,  H01L27/12 ,  H01L27/06 ,  H01L29/36

Abstract: An integrated circuit includes an insulating layer overlying a semiconductor substrate. A semiconductor layer of a first conductivity type overlies the insulating layer. A plurality of projecting regions that are spaced apart from each other overly the semiconductor layer. A sequence of PN junctions are in the semiconductor layer. Each PN junction is located at an edge of an associated projecting region. Each PN junction also extends vertically from an upper surface of the semiconductor layer to the insulating layer.

公开(公告)号：US10218336B2

公开(公告)日：2019-02-26

申请号：US15436817

申请日：2017-02-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: H03L7/099 ,  H03L5/00 ,  G05F3/26 ,  H03K3/03 ,  H03K3/011 ,  G11C7/06 ,  H03L1/00

Abstract: A device and method can be used to manage the operation of a ring oscillator circuit. A master oscillator circuit generates a master supply voltage. The master supply voltage associated with a stable oscillation rate of the master oscillator circuit. The master oscillator circuit is supplied with current and is structurally identical to the ring oscillator circuit. A capacitive circuit is loaded with a load voltage originating from the master supply voltage. In response to a control signal, the ring oscillator circuit is supplied with a current controlled by a voltage delivered by the capacitive circuit, in such a way as to provide a stable oscillation rate for the ring oscillator circuit.

公开(公告)号：US10215594B2

公开(公告)日：2019-02-26

申请号：US15379329

申请日：2016-12-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Vincent Onde

IPC: G01D5/249 ,  G01D4/00 ,  G01D5/347

Abstract: A rotary element is equipped with a pattern representing a reflected binary code on at least three bits. A detection circuit is configured to sense the pattern and deliver an incident signal encoded in reflected binary code on at least three bits. The incident signal is converted by a transcoding circuit into an intermediate signal encoded in reflected binary code on two bits. A decoding stage decodes the intermediate signal and outputs at least one clock signal representing the amount of rotation of the rotary element and a direction signal representing the direction of rotation. A processing circuit determines the movement of the rotary element, and has at least one general purpose timer designed to receive the at least one clock signal and direction signal.

公开(公告)号：US20190057981A1

公开(公告)日：2019-02-21

申请号：US16057466

申请日：2018-08-07

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Jean-Jacques FAGOT ,  Philippe BOIVIN ,  Franck ARNAUD

IPC: H01L27/12 ,  H01L21/84

Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.

公开(公告)号：US10210776B2

公开(公告)日：2019-02-19

申请号：US15046069

申请日：2016-02-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Bruneau

IPC: H04L9/00 ,  H04L9/06 ,  G09C1/00

Abstract: A method of protecting a Rijndael-type algorithm executed by an electronic circuit against side channel attacks, wherein: each block of data to be encrypted or to be decrypted is masked with a first mask before a non-linear block substitution operation is applied based on a substitution box, and is then unmasked with a second mask after the substitution; and the substitution box is recalculated, block by block, before the non-linear operation is applied, the processing order of the blocks of the substitution box being submitted to a random permutation, commutative with the non-linear substitution operation.

公开(公告)号：US10199368B2

公开(公告)日：2019-02-05

申请号：US15436819

申请日：2017-02-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/866 ,  H02H9/04

Abstract: An integrated circuit includes at least one input-output pad and a terminal intended to be connected to a source of a reference potential and further including a protection structure including a thyristor forward-connected between the pad and the terminal. The thyristor includes a first resistor between its cathode gate and the terminal. At least one Zener diode is disposed between the thyristor and the pad. The anode of the Zener diode is connected to the cathode gate of the thyristor and the cathode of the Zener diode is connected to the pad via at least one second resistor. The junction of the Zener diode is different from the junctions of the PNPN structure of the thyristor.

公开(公告)号：US20190027566A1

公开(公告)日：2019-01-24

申请号：US16036240

申请日：2018-07-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Julien DELALLEAU

IPC: H01L29/423 ,  H01L27/11521 ,  H01L29/78 ,  H01L29/788 ,  H01L21/28

CPC classification number: H01L29/42324 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/42376 ,  H01L29/66825 ,  H01L29/7835 ,  H01L29/788 ,  H01L29/7881

Abstract: A MOS transistor located in and on a semiconductor substrate has a drain region, a source region and a conductive gate region. The conductive gate region includes a first conductive gate region that is insulated from the semiconductor substrate and a second conductive gate region that is insulated from and located above the first conductive gate region. A length of the first conductive gate region, measured in the drain-source direction, is greater than a length of the second conductive gate region, also measured in the drain-source direction. The first conductive gate region protrudes longitudinally in the drain-source direction beyond the second conductive gate region at least on one side of the second conductive gate region so as to extend over at least one of the source and drain regions.