公开(公告)号：US10510662B2

公开(公告)日：2019-12-17

申请号：US15805282

申请日：2017-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chun Yu Wong ,  Kwan-Yong Lim ,  Seong Yeol Mun ,  Jagar Singh ,  Hui Zang

IPC: H01L21/76 ,  H01L23/525 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L21/3105

Abstract: One illustrative method disclosed herein comprises forming a vertically oriented semiconductor (VOS) structure in a semiconductor substrate and performing a metal silicide formation process to convert at least a portion of the VOS structure into a metal silicide material, thereby forming a conductive silicide vertically oriented e-fuse.

公开(公告)号：US10475890B2

公开(公告)日：2019-11-12

申请号：US15728070

申请日：2017-10-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Wei Zhao ,  Hui Zang ,  Hong Yu ,  Zhenyu Hu ,  Scott Beasor ,  Erik Geiss ,  Jerome Ciavatti ,  Jae Gon Lee

IPC: H01L29/417 ,  H01L27/11 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to scaled memory structures with middle of the line cuts and methods of manufacture The structure comprises: a plurality of fin structures formed on a substrate; a plurality of gate structures spanning over adjacent fin structures; a cut in adjacent epitaxial source/drain regions; and a cut in contact material formed adjacent to the plurality of gate structures, which provides separate contacts.

公开(公告)号：US20190326209A1

公开(公告)日：2019-10-24

申请号：US15959727

申请日：2018-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Xiaoqiang Zhang ,  Haizhou Yin ,  Moosung M. Chae ,  Jinping Liu ,  Hui Zang

IPC: H01L23/528 ,  H01L23/525 ,  H01L21/768

Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.

公开(公告)号：US10438955B2

公开(公告)日：2019-10-08

申请号：US15995896

申请日：2018-06-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L21/768 ,  H01L27/11 ,  H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L23/535

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices for forming conductive paths between fins for contact-to-gate shorting. One method includes, for instance: obtaining wafer with a substrate, at least one fin, at least one hard mask, and an oxide layer; etching the oxide layer to reveal at least one of a portion of the hard masks; forming sacrificial pillars over the substrate; forming sacrificial gates, wherein at least one sacrificial gate contacts at least one sacrificial pillar; growing an epitaxial layer between the at least one sacrificial gate and the at least one sacrificial pillar; starting a RMG process on the sacrificial gates; etching to remove the sacrificial pillars and form pillar openings; and completing the RMG process to fill the pillar openings and the gate openings with a metal.

公开(公告)号：US10431499B2

公开(公告)日：2019-10-01

申请号：US16134650

申请日：2018-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guowei Xu ,  Hui Zang ,  Haiting Wang ,  Yue Zhong

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/027

Abstract: One illustrative integrated circuit product disclosed herein includes a first final gate structure for a first transistor device, a second final gate structure for a second transistor device, the first and second transistors having a gate width direction and a gate length direction that is substantially normal to the gate width direction, and an insulating gate separation structure positioned between the first and second final gate structures, the insulating gate separation structure comprising an upper portion and a lower portion, the lower portion having a first lateral width in the gate width direction that is substantially uniform throughout a vertical height of the lower portion, the upper portion having a substantially uniform second lateral width in the gate width direction that is substantially uniform throughout a vertical height of the upper portion, wherein the second lateral width is less than the first lateral width.

公开(公告)号：US10418455B2

公开(公告)日：2019-09-17

申请号：US15716287

申请日：2017-09-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Daniel Jaeger ,  Haigou Huang ,  Veeraraghavan Basker ,  Christopher Nassar ,  Jinsheng Gao ,  Michael Aquilino

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L21/321 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L27/092

Abstract: At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.

公开(公告)号：US10418285B1

公开(公告)日：2019-09-17

申请号：US15993142

申请日：2018-05-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Chun Yu Wong ,  Laertis Economikos

IPC: H01L29/06 ,  H01L21/8234

Abstract: Methods of forming a CT pillar with reduced width and increased distance from neighboring fins and the resulting devices are provided. Embodiments include providing a first pair of fins and a second pair of fins in an oxide layer, wherein the first and second pair of fins include Si; and forming a CT pillar including SiN between the first and second pair of fins and over a portion of the oxide layer, wherein width of the CT pillar and distance between the CT pillar and the first and second pair of fins are inversely proportional.

公开(公告)号：US10410933B2

公开(公告)日：2019-09-10

申请号：US15602225

申请日：2017-05-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Hui Zang ,  Guowei Xu

IPC: H01L21/3213 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06 ,  H01L21/02

Abstract: This disclosure relates to a method of replacement metal gate patterning for nanosheet devices including: forming a first and a second nanosheet stack on a substrate, the first and the second nanosheet stacks being adjacent to each other and each including vertically adjacent nanosheets separated by a distance; depositing a first metal surrounding the first nanosheet stack and a second portion of the first metal surrounding the second nanosheet stack; forming an isolation region between the first nanosheet stack and the second nanosheet stack; removing the second portion of the first metal surrounding the second nanosheet stack with an etching process, the isolation region preventing the etching process from reaching the first portion of the first metal and thereby preventing removal of the first portion of the first metal; and depositing a second metal surrounding each of the nanosheets of the second nanosheet stack.

公开(公告)号：US10396000B2

公开(公告)日：2019-08-27

申请号：US14789476

申请日：2015-07-01

Applicant: International Business Machines Corporation ,  Globalfoundries, Inc.

Inventor： Tenko Yamashita ,  Chun-Chen Yeh ,  Hui Zang

IPC: H01L21/66 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.

公开(公告)号：US20190244865A1

公开(公告)日：2019-08-08

申请号：US16134650

申请日：2018-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guowei Xu ,  Hui Zang ,  Haiting Wang ,  Yue Zhong

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L27/02 ,  H01L27/088 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L21/823437 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/0274 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/66545

Abstract: One illustrative integrated circuit product disclosed herein includes a first final gate structure for a first transistor device, a second final gate structure for a second transistor device, the first and second transistors having a gate width direction and a gate length direction that is substantially normal to the gate width direction, and an insulating gate separation structure positioned between the first and second final gate structures, the insulating gate separation structure comprising an upper portion and a lower portion, the lower portion having a first lateral width in the gate width direction that is substantially uniform throughout a vertical height of the lower portion, the upper portion having a substantially uniform second lateral width in the gate width direction that is substantially uniform throughout a vertical height of the upper portion, wherein the second lateral width is less than the first lateral width.