公开(公告)号：US20160133719A1

公开(公告)日：2016-05-12

申请号：US14535852

申请日：2014-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/32 ,  H01L21/3213 ,  H01L21/3205

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/31111 ,  H01L21/32 ,  H01L21/32055 ,  H01L21/32133 ,  H01L21/32139 ,  H01L29/66553

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin having an upper surface and a plurality of side surfaces, forming a sacrificial gate structure comprised of a low-density oxide material having a density of less than 1.8 g/cm3 on and in contact with the upper surface and the side surfaces of the fin and a sacrificial gate material positioned on and in contact with the upper surface of the low-density oxide material, and forming a sidewall spacer adjacent the sacrificial gate structure. The method further includes removing the sacrificial gate material so as to thereby expose the low-density oxide material, so as to define a replacement gate cavity, and forming a replacement gate structure in the replacement gate cavity.

Abstract translation: 本文公开的一种说明性方法包括形成具有上表面和多个侧表面的翅片，形成牺牲栅极结构，所述牺牲栅极结构由密度小于1.8g / cm 3的低密度氧化物材料和 与翅片的上表面和侧表面接触，并且牺牲栅材料定位在低密度氧化物材料的上表面上并与低密度氧化物材料的上表面接触，并且形成邻近牺牲栅极结构的侧壁间隔物。 该方法还包括去除牺牲栅极材料，从而暴露低密度氧化物材料，以便限定替换栅极腔，并在替换栅极腔中形成替代栅极结构。

公开(公告)号：US09306001B1

公开(公告)日：2016-04-05

申请号：US14685745

申请日：2015-04-14

Applicant: International Business Machines Corporation ,  Globalfoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/761 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L27/12 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L29/0638 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Embodiments are directed to a method of forming a leakage current stopper of a fin-type field effect transistor (FinFET). The method includes forming at least one fin having an active region, a non-active region and a channel region in the active region. The method further includes exposing a surface of the non-active region, wherein the exposed surface leads to a portion of the non-active region that is substantially underneath the channel region. The method further includes implanting dopants through the exposed surface of the non-active region to form the leakage current stopper region.

Abstract translation: 实施例涉及一种形成鳍式场效应晶体管（FinFET）的漏电流阻挡器的方法。 该方法包括在有源区中形成至少一个具有有源区，非有源区和沟道区的鳍。 该方法还包括暴露非有源区的表面，其中暴露的表面导致基本上在沟道区下面的非有源区的一部分。 该方法还包括通过非有源区的暴露表面注入掺杂剂以形成泄漏电流停止区。

公开(公告)号：US20160093692A1

公开(公告)日：2016-03-31

申请号：US14962015

申请日：2015-12-08

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/06 ,  H01L29/423 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A device includes first and second fins defined in a semiconductor substrate and a raised isolation post structure positioned between the first and second fins, wherein an upper surface of the raised isolation post structure is at a level that is approximately equal to or greater than a level corresponding to an upper surface of each of the first and second fins. A first space is defined by a sidewall of the first fin and a first sidewall of the raised isolation post structure, a second space is defined by a sidewall of the second fin and a second sidewall of the raised isolation post structure, and a gate structure is positioned around a portion of each of the first and second fins and around a portion of the raised isolation post structure, wherein at least portions of the gate structure are positioned in the first and second spaces.

Abstract translation: 一种装置包括限定在半导体衬底中的第一和第二鳍片和位于第一鳍片和第二鳍片之间的凸起隔离柱结构，其中凸起隔离柱结构的上表面处于大致等于或大于水平面的水平面 对应于第一和第二鳍片中的每一个的上表面。 第一空间由第一鳍片的侧壁和凸起隔离柱结构的第一侧壁限定，第二空间由第二鳍片的侧壁和凸起隔离柱结构的第二侧壁限定，以及栅极结构 围绕所述第一和第二鳍片中的每一个的一部分并且围绕所述凸起隔离柱结构的一部分定位，其中所述栅极结构的至少部分位于所述第一和第二空间中。

公开(公告)号：US09269815B2

公开(公告)日：2016-02-23

申请号：US14333135

申请日：2014-07-16

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/785

Abstract: One method disclosed herein includes forming a conformal liner layer in a plurality of trenches that define a fin, forming a layer of insulating material above the liner layer, exposing portions of the liner layer, removing portions of the liner layer so as to result in a generally U-shaped liner positioned at a bottom of each of the trenches, performing at least one third etching process on the layer of insulating material, wherein at least a portion of the layer of insulating material is positioned within a cavity of the U-shaped liner layer, and forming a gate structure around the fin. A FinFET device disclosed herein includes a plurality of trenches that define a fin, a local isolation that includes a generally U-shaped liner that defines, in part, a cavity and a layer of insulating material positioned within the cavity, and a gate structure positioned around the fin.

Abstract translation: 本文公开的一种方法包括在限定翅片的多个沟槽中形成共形衬垫层，在衬垫层上方形成绝缘材料层，暴露衬里层的部分，去除衬里层的部分，从而导致 大体呈U形的衬垫，位于每个沟槽的底部，对绝缘材料层进行至少一个第三蚀刻工艺，其中绝缘材料层的至少一部分位于U形的空腔内 衬垫层，并且在翅片周围形成栅极结构。 本文公开的FinFET器件包括限定翅片的多个沟槽，局部隔离，其包括大致U形的衬垫，其部分地限定腔体中定位的空腔和绝缘材料层，以及定位的门结构 围绕翅膀

公开(公告)号：US20160027700A1

公开(公告)日：2016-01-28

申请号：US14876212

申请日：2015-10-06

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Ali Khakifirooz ,  Theodorus E. Standaert ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L29/417 ,  H01L21/311

CPC classification number: H01L21/823437 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785

Abstract: A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.

公开(公告)号：US09236557B2

公开(公告)日：2016-01-12

申请号：US14156210

申请日：2014-01-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Ruilong Xie ,  Xiuyu Cai ,  Hyun-Jin Cho

IPC: H01L21/00 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L43/12

Abstract: Embodiments herein provide a magnetic tunnel junction (MTJ) formed between metal layers of a semiconductor device. Specifically, provided is an approach for forming the semiconductor device using only one or two masks, the approach comprising: forming a first metal layer in a dielectric layer of the semiconductor device, forming a bottom electrode layer over the first metal layer, forming a MTJ over the bottom electrode layer, forming a top electrode layer over the MTJ, patterning the top electrode layer and the MTJ with a first mask, and forming a second metal layer over the top electrode layer. Optionally, the bottom electrode layer may be patterned using a second mask. Furthermore, in another embodiment, an insulator layer (e.g., manganese) is formed atop the dielectric layer, wherein a top surface of the first metal layer remains exposed following formation of the insulator layer such that the bottom electrode layer contacts the top surface of the first metal layer. By forming the MTJ between the metal layers using only one or two masks, the overall number of processing steps is reduced.

Abstract translation: 本文的实施例提供了形成在半导体器件的金属层之间的磁性隧道结（MTJ）。 具体地，提供了仅使用一个或两个掩模形成半导体器件的方法，所述方法包括：在所述半导体器件的电介质层中形成第一金属层，在所述第一金属层上形成底部电极层，形成MTJ 在所述底部电极层上方，在所述MTJ上形成顶部电极层，用第一掩模图案化所述顶部电极层和所述MTJ，以及在所述顶部电极层上方形成第二金属层。 可选地，可以使用第二掩模对底部电极层进行图案化。 此外，在另一个实施例中，绝缘体层（例如，锰）形成在电介质层的顶部，其中第一金属层的顶表面在形成绝缘体层之后保持暴露，使得底部电极层接触绝缘层的顶表面 第一金属层。 通过仅使用一个或两个掩模在金属层之间形成MTJ，减少了处理步骤的总数。

公开(公告)号：US20150372140A1

公开(公告)日：2015-12-24

申请号：US14308045

申请日：2014-06-18

Applicant: STMicroelectronics, Inc ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L29/78 ,  H01L21/306 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/30625 ,  H01L21/3083 ,  H01L21/311 ,  H01L21/31144 ,  H01L29/66818 ,  H01L29/785

Abstract: Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.

Abstract translation: 描述了用于控制finFET鳍片的回蚀的技术和结构。 一个或多个层可以沉积在翅片上并被蚀刻。 可以使用平坦化层的蚀刻来确定邻近鳍片的一个或多个层的自限制蚀刻高度以及翅片的自限制蚀刻高度。 应变诱发材料可以形成在蚀刻翅片的区域，以引起finFET通道中的应变。

公开(公告)号：US20150364326A1

公开(公告)日：2015-12-17

申请号：US14301864

申请日：2014-06-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Xiuyu Cai

IPC: H01L21/28 ,  H01L29/51

CPC classification number: H01L29/4232 ,  H01L21/31144 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/78

Abstract: One illustrative method disclosed herein includes, among other things, forming a first high-k protection layer on the source/drain regions and adjacent the sidewall spacers of a transistor device, removing a sacrificial gate structure positioned between the sidewall spacers so as to thereby define a replacement gate cavity, forming a replacement gate structure in the replacement gate cavity, forming a second high-k protection layer above an upper surface of the spacers, above an upper surface of the replacement gate structure and above the first high-k protection layer, and removing portions of the second high-k protection layer positioned above the first high-k protection layer.

Abstract translation: 本文公开的一种说明性方法包括在源极/漏极区域上并且邻近晶体管器件的侧壁间隔物处形成第一高k保护层，去除位于侧壁间隔物之间​​的牺牲栅极结构，从而限定 替换栅极腔，在替换栅极腔中形成替代栅极结构，在替代栅极结构的上表面上方并在第一高k保护层上方形成位于间隔物上表面上方的第二高k保护层 以及去除位于第一高k保护层上方的第二高k保护层的部分。

公开(公告)号：US20150349083A1

公开(公告)日：2015-12-03

申请号：US14289737

申请日：2014-05-29

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/51 ,  H01L29/66 ,  H01L21/3213 ,  H01L49/02 ,  H01L21/02 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L23/535 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/285 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5283 ,  H01L23/53266 ,  H01L29/6659 ,  H01L29/66643 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method disclosed includes, among other things, conformably depositing a layer of contact insulating material and a conductive material layer in a contact opening, forming a reduced-thickness sacrificial material layer in the contact opening so as to expose a portion, but not all, of the conductive material layer, removing portions of the conductive material layer and the layer of contact insulating material positioned above the upper surface of the reduced-thickness sacrificial material layer, removing the reduced-thickness sacrificial material layer, and forming a conductive contact in the contact opening that contacts the recessed portions of the conductive material layer and the layer of contact insulating material.

Abstract translation: 所公开的一种方法包括在接触开口中顺应地沉积接触绝缘材料层和导电材料层，在接触开口中形成减小厚度的牺牲材料层，以暴露部分，但不是全部， 的导电材料层的去除部分，去除部分导电材料层和接触绝缘材料层位于减薄厚度的牺牲材料层的上表面之上，去除减薄的牺牲材料层，并在其中形成导电接触 接触开口，其接触导电材料层的凹部和接触绝缘材料层。

公开(公告)号：US09196696B2

公开(公告)日：2015-11-24

申请号：US14260913

申请日：2014-04-24

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L23/48 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L21/3213

CPC classification number: H01L29/4958 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/32135 ,  H01L29/4966 ,  H01L29/66545

Abstract: Integrated circuits with improved gate uniformity and methods for fabricating such integrated circuits are provided. In an embodiment, an integrated circuit includes a semiconductor substrate and a replacement metal gate structure overlying the semiconductor substrate. The replacement metal gate structure includes a first metal and a second metal and has a recess surface formed by the first metal and the second metal. The first metal and the second metal include a first species of diffused foreign ions. The integrated circuit further includes a metal fill material overlying the recess surface formed by the first metal and the second metal.

Abstract translation: 提供了具有改善的栅极均匀性的集成电路以及用于制造这种集成电路的方法。 在一个实施例中，集成电路包括覆盖半导体衬底的半导体衬底和替换金属栅极结构。 替代金属栅极结构包括第一金属和第二金属，并且具有由第一金属和第二金属形成的凹陷表面。 第一金属和第二金属包括扩散的外来离子的第一种。 集成电路还包括覆盖由第一金属和第二金属形成的凹陷表面的金属填充材料。