公开(公告)号：US10217799B2

公开(公告)日：2019-02-26

申请号：US15686389

申请日：2017-08-25

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/24 ,  H01L27/1158 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11553 ,  H01L45/00

Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

公开(公告)号：US10157926B2

公开(公告)日：2018-12-18

申请号：US15664161

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Gloria Yang ,  Suraj J. Mathew ,  Raghunath Singanamalla ,  Vinay Nair ,  Scott J. Derner ,  Michael Amiel Shore ,  Brent Keeth ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/423 ,  H01L29/78 ,  G11C11/403 ,  H01L23/528 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

公开(公告)号：US20180350827A1

公开(公告)日：2018-12-06

申请号：US15980503

申请日：2018-05-15

Applicant: Micron Technology, Inc.

Inventor： Charles H. Dennison ,  Akira Goda ,  John Hopkins ,  Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/11556 ,  H01L29/66 ,  H01L27/11578 ,  H01L21/28

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L27/11578 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

公开(公告)号：US10090317B2

公开(公告)日：2018-10-02

申请号：US15221131

申请日：2016-07-27

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Zhenyu Lu ,  Roger W. Lindsay ,  Brian Cleereman ,  John Hopkins ,  Hongbin Zhu ,  Fatma Arzum Simsek-Ege ,  Prasanna Srinivasan ,  Purnima Narayanan

IPC: H01L21/3205 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L29/66 ,  H01L29/788 ,  G11C16/04 ,  H01L27/1157

Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.

公开(公告)号：US09899413B2

公开(公告)日：2018-02-20

申请号：US15472052

申请日：2017-03-28

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Fatma Arzum Simsek-Ege

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/02 ,  H01L21/28 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02244 ,  H01L21/02274 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.

公开(公告)号：US20170365615A1

公开(公告)日：2017-12-21

申请号：US15691477

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Charles H. Dennison ,  Akira Goda ,  John Hopkins ,  Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/11556 ,  H01L21/28 ,  H01L27/11578 ,  H01L29/66

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L27/11578 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

公开(公告)号：US09773841B2

公开(公告)日：2017-09-26

申请号：US15056548

申请日：2016-02-29

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L29/06 ,  H01L27/24 ,  H01L27/1158 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11553 ,  H01L45/00

CPC classification number: H01L27/2454 ,  H01L27/11553 ,  H01L27/1158 ,  H01L27/2481 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H01L45/1608

Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

公开(公告)号：US09634025B2

公开(公告)日：2017-04-25

申请号：US15248968

申请日：2016-08-26

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Fatma Arzum Simsek-Ege

IPC: H01L21/8242 ,  H01L29/76 ,  H01L27/11582 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02244 ,  H01L21/02274 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.

公开(公告)号：US20160133638A1

公开(公告)日：2016-05-12

申请号：US14536021

申请日：2014-11-07

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat ,  Luan C. Tran ,  Meng-Wei Kuo ,  Yushi Hu

IPC: H01L27/115

CPC classification number: H01L27/11524 ,  H01L21/8221 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/11582

Abstract: Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.

Abstract translation: 一些实施例包括具有源材料，源材料上方的介电材料，介电材料上方的选择栅极材料，选择栅极材料上方的存储单元堆叠，位于介电材料的开口中的导电插塞的装置和方法，以及 接触源材料的一部分，以及延伸穿过存储单元堆叠和选择栅极材料并与导电插塞接触的沟道材料。

公开(公告)号：US09276011B2

公开(公告)日：2016-03-01

申请号：US13838579

申请日：2013-03-15

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/2454 ,  H01L27/11553 ,  H01L27/1158 ,  H01L27/2481 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H01L45/1608

Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

Abstract translation: 各种实施例包括诸如具有连续单元柱的存储器堆叠的装置和方法。 在各种实施例中，该装置包括源材料，缓冲材料，选择栅极漏极（SGD）以及布置在源材料和SGD之间的存储堆叠。 存储器堆叠包括交替电平的导体材料和电介质材料。 连续的通道填充材料形成从源材料连续到至少与SGD相对应的水平的细胞柱。