公开(公告)号：US11342334B2

公开(公告)日：2022-05-24

申请号：US16901885

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Chi On Chui ,  Yu-Ming Lin

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/423

Abstract: An improved memory cell architecture including a nanostructure field-effect transistor (nano-FET) and a horizontal capacitor extending at least partially under the nano-FET and methods of forming the same are disclosed. In an embodiment, semiconductor device includes a channel structure over a semiconductor substrate; a gate structure encircling the channel structure; a first source/drain region adjacent the gate structure; and a capacitor adjacent the first source/drain region, the capacitor extending under the first source/drain region and the gate structure in a cross-sectional view.

公开(公告)号：US11333827B2

公开(公告)日：2022-05-17

申请号：US16806043

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chang Chang ,  Meng-Han Lin

IPC: G02B6/124 ,  H01L23/48 ,  G02B6/136 ,  G02B6/12

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a protective ring structure overlying a grating coupler structure. A waveguide structure is disposed within a semiconductor substrate and comprises the grating coupler structure. An interconnect structure overlies the semiconductor substrate. The interconnect structure includes a contact etch stop layer (CESL) and a conductive contact over the semiconductor substrate. The conductive contact extends through the CESL. The protective ring structure extends through the CESL and has an upper surface aligned with an upper surface of the conductive contact.

公开(公告)号：US20220037361A1

公开(公告)日：2022-02-03

申请号：US17112606

申请日：2020-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L23/522 ,  H01L27/1159

Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

公开(公告)号：US11217597B2

公开(公告)日：2022-01-04

申请号：US16585809

申请日：2019-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Ching-Wen Chan

IPC: H01L27/11548 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11519

Abstract: In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. In the method, a protrusion of a substrate is formed in the ring structure area. The protrusion protrudes from an isolation insulating layer. A high-k dielectric film is formed, thereby covering the protrusion and the isolation insulating layer. A poly silicon film is formed over the high-k dielectric film. The poly silicon film and the high-k dielectric film are patterned. Insulating layers are formed over the patterned poly silicon film and high-k dielectric film, thereby sealing the patterned high-k dielectric film.

公开(公告)号：US20210408046A1

公开(公告)日：2021-12-30

申请号：US17125435

申请日：2020-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Chang ,  Meng-Han Lin ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin

IPC: H01L27/11597 ,  H01L27/11587 ,  G11C11/22 ,  H01L29/78

Abstract: A memory cell includes a transistor including a memory film extending along a word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film; a bit line extending along the memory film, wherein the memory film is between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film; and an isolation region between the source line and the bit line.

公开(公告)号：US20210271023A1

公开(公告)日：2021-09-02

申请号：US16806043

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chang Chang ,  Meng-Han Lin

IPC: G02B6/12 ,  H01L23/48

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a protective ring structure overlying a grating coupler structure. A waveguide structure is disposed within a semiconductor substrate and comprises the grating coupler structure. An interconnect structure overlies the semiconductor substrate. The interconnect structure includes a contact etch stop layer (CESL) and a conductive contact over the semiconductor substrate. The conductive contact extends through the CESL. The protective ring structure extends through the CESL and has an upper surface aligned with an upper surface of the conductive contact.

公开(公告)号：US11069693B2

公开(公告)日：2021-07-20

申请号：US16545713

申请日：2019-08-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Wei Cheng Wu

IPC: H01L29/423 ,  H01L21/28 ,  H01L27/105 ,  H01L29/66 ,  H01L27/11521 ,  H01L27/11548 ,  H01L27/11526

Abstract: A method is provided for the manufacture of an integrated semiconductor device that includes an embedded flash memory array formed in a recessed region of a semiconductor substrate, the method includes, prior to formation of floating and control gate stacks of the memory array, depositing a protective layer over layers of gate material, and depositing a self-leveling sacrificial layer over the protective layer to produce a substantially planar upper surface. The sacrificial layer is then etched to a depth that removes the sacrificial layer and leaves a substantially planar face on the protective layer. A photo mask is then deposited on the protective layer and the gate stacks are etched from the layers of gate material.

公开(公告)号：US11031409B2

公开(公告)日：2021-06-08

申请号：US16574220

申请日：2019-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Wei Cheng Wu ,  Chih-Pin Huang

IPC: H01L27/11548 ,  H01L29/423 ,  H01L29/66 ,  H01L23/532 ,  H01L27/11524 ,  H01L21/768 ,  H01L21/033 ,  H01L21/762 ,  H01L21/321

Abstract: Various embodiments of the present application are directed to an embedded memory boundary structure with a boundary sidewall spacer, and associated forming methods. In some embodiments, an isolation structure is disposed in a semiconductor substrate to separate a memory region from a logic region. A memory cell structure is disposed on the memory region and a cell boundary structure is formed on the isolation structure including a boundary sidewall spacer. A protecting dielectric layer is disposed on a top surface of the boundary sidewall spacer. The boundary sidewall spacer and the protecting dielectric layer provide a smooth boundary sidewall that is not subject to damage during formation of the logic device structure and, hence, is not subject to trapping high κ etch residue during formation of the logic device structure with HKMG technology.

公开(公告)号：US20210082932A1

公开(公告)日：2021-03-18

申请号：US17104686

申请日：2020-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L27/11536 ,  H01L29/788 ,  H01L29/423 ,  H01L29/49 ,  H01L29/08 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/027 ,  H01L27/11521

Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A memory cell structure is disposed on the memory region. A logic device is disposed on the logic region having a logic gate electrode separated from the substrate by a logic gate dielectric. A sidewall spacer is disposed along a sidewall surface of the logic gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with sidewall surfaces of the pair of select gate electrodes within the memory region, and extending upwardly along the sidewall spacer within the logic region.

公开(公告)号：US10804281B2

公开(公告)日：2020-10-13

申请号：US16169156

申请日：2018-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Chen-Chin Liu ,  Chih-Pin Huang

IPC: H01L29/78 ,  H01L27/11548 ,  H01L27/11519 ,  H01L27/11529 ,  H01L29/423 ,  H01L29/51 ,  H01L21/033 ,  H01L21/321 ,  H01L21/308 ,  H01L21/28 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11573

Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate having a peripheral region and a memory cell region separated by an isolation structure. The isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material. A logic device is arranged on the peripheral region. A memory device is arranged on the memory region. The memory device includes a gate electrode and a memory hardmask over the gate electrode. An anti-dishing structure is disposed on the isolation structure. An upper surface of the anti-dishing structure and an upper surface of the memory hardmask have equal heights as measured from the top surface of the semiconductor substrate.