公开(公告)号：US08329515B2

公开(公告)日：2012-12-11

申请号：US12647888

申请日：2009-12-28

Applicant: Bin Yang ,  Man Fai Ng

Inventor： Bin Yang ,  Man Fai Ng

IPC: H01L21/82

CPC classification number: H01L27/0629 ,  H01L21/823807 ,  H01L21/823814 ,  H01L23/5256 ,  H01L29/4925 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An eFUSE is formed with a gate stack including a layer of embedded silicon germanium (eSiGe) on the polysilicon. An embodiment includes forming a shallow trench isolation (STI) region in a substrate, forming a first gate stack on the substrate for a PMOS device, forming a second gate stack on an STI region for an eFUSE, forming first embedded silicon germanium (eSiGe) on the substrate on first and second sides of the first gate stack, and forming second eSiGe on the second gate stack. The addition of eSiGe to the eFUSE gate stack increases the distance between the eFUSE debris zone and an underlying metal gate, thereby preventing potential shorting.

Abstract translation: 在多晶硅上形成包括一层嵌入硅锗（eSiGe）的栅极堆叠的eFUSE。 一个实施例包括在衬底中形成浅沟槽隔离（STI）区域，在用于PMOS器件的衬底上形成第一栅极堆叠，在用于eFUSE的STI区域上形成第二栅极堆叠，形成第一嵌入硅锗（eSiGe） 在第一栅极堆叠的第一和第二侧上的衬底上，并且在第二栅极堆叠上形成第二eSiGe。 将eSiGe添加到eFUSE栅极堆叠中增加了eFUSE碎片区域和底层金属栅极之间的距离，从而防止了潜在的短路。

公开(公告)号：US20120305940A1

公开(公告)日：2012-12-06

申请号：US13151238

申请日：2011-06-01

Applicant: Thomas N. Adam ,  Stephen W. Bedell ,  Bruce B. Doris ,  Lisa F. Edge ,  Keith E. Fogel ,  Johnathan E. Faltermeier ,  Jinghong Li ,  Alexander Reznicek ,  Devendra K. Sadana ,  Bin Yang

Inventor： Thomas N. Adam ,  Stephen W. Bedell ,  Bruce B. Doris ,  Lisa F. Edge ,  Keith E. Fogel ,  Johnathan E. Faltermeier ,  Jinghong Li ,  Alexander Reznicek ,  Devendra K. Sadana ,  Bin Yang

IPC: H01L29/24 ,  H01L21/20

CPC classification number: H01L21/02529 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78654

Abstract: A method and structure are disclosed for a defect free Si:C source/drain in an NFET device. A wafer is accepted with a primary surface of {100} crystallographic orientation. A recess is formed in the wafer in such manner that the bottom surface and the four sidewall surfaces of the recess are all having {100} crystallographic orientations. A Si:C material is eptaxially grown in the recess, and due to the crystallographic orientations the defect density next to each of the four sidewall surfaces is essentially the same as next to the bottom surface. The epitaxially filled recess is used in the source/drain fabrication of an NFET device. The NFET device is oriented along the crystallographic direction, and has the device channel under a tensile strain due to the defect free Si:C in the source/drain.

Abstract translation: 公开了在NFET器件中的无缺陷Si：C源极/漏极的方法和结构。 接受具有{100}晶体取向的主表面的晶片。 以这样的方式在晶片中形成凹部，使得凹部的底表面和四个侧壁表面都具有{100}晶体取向。 Si：C材料在凹槽中被轴向生长，并且由于晶体取向，邻近四个侧壁表面的缺陷密度基本上与下表面相同。 外延填充的凹槽用于NFET器件的源极/漏极制造。 NFET器件沿着<100>结晶方向取向，由于源极/漏极中的缺陷Si：C，器件沟道处于拉伸应变状态。

公开(公告)号：US20120295439A1

公开(公告)日：2012-11-22

申请号：US13564181

申请日：2012-08-01

Applicant: Christian Lavoie ,  Tak H. Ning ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

Inventor： Christian Lavoie ,  Tak H. Ning ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

IPC: H01L21/3205

CPC classification number: H01L21/28518

Abstract: In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.

Abstract translation: 在一个示例性实施例中，一种可由机器读取的程序存储设备，其有形地体现了可由机器执行的用于执行操作的指令程序，所述操作包括：在半导体结构的表面上沉积具有第一金属的第一层， 第一层在第一层和半导体结构的界面处形成第一混合区; 去除沉积的第一层的一部分以暴露第一混合区; 在所述第一混合区域上沉积具有第二金属的第二层，其中沉积所述第二层在所述第二层和所述第一混合区的界面处产生第二混合区; 去除沉积的第二层的一部分以暴露第二混合区; 以及在所述半导体结构上执行至少一个退火。

公开(公告)号：US08294211B2

公开(公告)日：2012-10-23

申请号：US12687610

申请日：2010-01-14

Applicant: Bin Yang ,  Rohit Pal ,  Michael Hargrove

Inventor： Bin Yang ,  Rohit Pal ,  Michael Hargrove

IPC: H01L29/786

CPC classification number: H01L27/12 ,  H01L21/84 ,  H01L21/845 ,  H01L23/485 ,  H01L27/1211

Abstract: A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.

Abstract translation: 此处提供制造具有背面导电插头的半导体器件的方法。 该方法通过形成覆盖绝缘体上半导体（SOI）衬底的栅极结构开始。 SOI衬底具有支撑层，覆盖在支撑层上的绝缘层，覆盖绝缘层的有源半导体区域和有源半导体区域外侧的隔离区域。 栅极结构的第一部分形成在隔离区域的上方，栅极结构的第二部分形成在有源半导体区域的上方。 该方法通过在有源半导体区域中形成源极/漏极区域继续，然后从SOI衬底去除支撑层。 接下来，该方法形成用于栅极结构和源极/漏极区域的导电插塞，其中每个导电插塞穿过绝缘层。

公开(公告)号：US08222093B2

公开(公告)日：2012-07-17

申请号：US12707150

申请日：2010-02-17

Applicant: Man Fai Ng ,  Bin Yang

Inventor： Man Fai Ng ,  Bin Yang

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/76

CPC classification number: H01L21/84 ,  H01L21/76267 ,  H01L21/823878 ,  H01L29/66772

Abstract: Methods and devices are provided for fabricating a semiconductor device having barrier regions within regions of insulating material resulting in outgassing paths from the regions of insulating material. A method comprises forming a barrier region within an insulating material proximate the isolated region of semiconductor material and forming a gate structure overlying the isolated region of semiconductor material. The barrier region is adjacent to the isolated region of semiconductor material, resulting in an outgassing path within the insulating material.

Abstract translation: 提供了用于制造在绝缘材料区域内具有阻挡区域的半导体器件的方法和装置，导致从绝缘材料区域的脱气路径。 一种方法包括在靠近半导体材料的隔离区域的绝缘材料内形成阻挡区域，并形成覆盖半导体材料的隔离区域的栅极结构。 阻挡区域与半导体材料的隔离区域相邻，导致绝缘材料内的除气路径。

公开(公告)号：US08178414B2

公开(公告)日：2012-05-15

申请号：US12632351

申请日：2009-12-07

Applicant: Bin Yang ,  Bo Bai

Inventor： Bin Yang ,  Bo Bai

IPC: H01L21/02

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833

Abstract: An NMOS transistor is formed with improved manufacturability. An embodiment includes forming N-type doped embedded silicon germanium containing carbon (eSiGe:C) in source/drain regions of a substrate, and amorphizing the eSiGe:C. The use of eSiGe:C provides a reduction in extension silicon and dopant loss, improved morphology, increased wafer throughput, improved short channel control, and reduced silicide to source/drain contact resistance.

Abstract translation: 形成具有改进的可制造性的NMOS晶体管。 实施例包括在衬底的源极/漏极区域中形成含有N型掺杂的含硅锗（eSiGe：C），并使eSiGe：C非晶化。 eSiGe：C的使用提供了延长硅和掺杂剂损耗的减少，改进的形态，增加的晶片产量，改进的短沟道控制以及降低的硅化物到源/漏接触电阻。

公开(公告)号：US20120112292A1

公开(公告)日：2012-05-10

申请号：US12940394

申请日：2010-11-05

Applicant: CHRISTIAN LAVOIE ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

Inventor： CHRISTIAN LAVOIE ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

IPC: H01L27/118 ,  H01L21/44

CPC classification number: H01L29/7833 ,  H01L21/26566 ,  H01L21/28518 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7843

Abstract: A method for forming an alternate conductive path in semiconductor devices includes forming a silicided contact in a source/drain region adjacent to an extension diffusion region and removing sidewall spacers from a gate structure. A metal layer is formed over a portion of the extension diffusion region in a substrate layer to intermix metal from the metal layer with the portion of the extension region without annealing the metal layer. An unmixed portion of the metal layer is removed. The alternate conductive path is formed on the extension diffusion region with intermixed metal by thermal processing after the unmixed portion of the metal layer has been removed.

Abstract translation: 在半导体器件中形成交替导电路径的方法包括在与延伸扩散区相邻的源极/漏极区域中形成硅化物接触，并从栅极结构去除侧壁间隔物。 在衬底层中的延伸扩散区域的一部分上形成金属层，以将来自金属层的金属与延伸区域的部分混合，而不退火金属层。 除去金属层的未混合部分。 在去除了金属层的未混合部分之后，通过热处理在互补导电路径上形成具有混合金属的延伸扩散区域。

公开(公告)号：US20110316093A1

公开(公告)日：2011-12-29

申请号：US12821507

申请日：2010-06-23

Applicant: Bin Yang ,  Man Fai NG

Inventor： Bin Yang ,  Man Fai NG

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7816 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7833

Abstract: A short channel semiconductor device is formed with halo regions that are separated from the bottom of the gate electrode and from each other. Embodiments include implanting halo regions after forming source/drain regions and source/drain extension regions. An embodiment includes forming source/drain extension regions in a substrate, forming source/drain regions in the substrate, forming halo regions under the source/drain extension regions, after forming the source drain regions, and forming a gate electrode on the substrate between the source/drain regions. By forming the halo regions after the high temperature processing involved informing the source/drain and source/drain extension regions, halo diffusion is minimized, thereby maintaining sufficient distance between halo regions and reducing short channel NMOS Vt roll-off.

Abstract translation: 短沟道半导体器件形成有与栅电极的底部彼此分离的晕圈。 实施例包括在形成源极/漏极区域和源极/漏极延伸区域之后注入晕圈。 一个实施例包括在衬底中形成源极/漏极延伸区域，在衬底中形成源极/漏极区域，在形成源极漏极区域之后在源极/漏极延伸区域下方形成卤素区域，以及在衬底上形成栅极电极 源/漏区。 通过在涉及源极/漏极和源极/漏极延伸区域的高温处理之后形成晕圈区域，使得光晕扩散最小化，从而在晕圈区域之间保持足够的距离并且减少短沟道NMOS Vt滚降。

公开(公告)号：US20110303009A1

公开(公告)日：2011-12-15

申请号：US13015927

申请日：2011-01-28

Applicant: Bin Yang ,  Zhen-kui Meng ,  Rui Zhang ,  Zhou Ge ,  Yi-lin Yan

Inventor： Bin Yang ,  Zhen-kui Meng ,  Rui Zhang ,  Zhou Ge ,  Yi-lin Yan

IPC: G01P15/125

CPC classification number: G01P15/125 ,  G01P15/18

Abstract: An tri-axis accelerometer is disclosed. The tri-axis accelerometer includes a mass, a first group of capacitance, a third group of capacitance being neighbor to the first group of capacitance. The mass defines an upper surface, a lower surface parallel to the upper surface and a side wall connecting the upper surface and the lower surface. The first group of capacitance includes a first movable electrode and the third group of capacitance includes a third movable electrode. The first movable electrode is perpendicular to the third movable electrode.

Abstract translation: 公开了三轴加速度计。 三轴加速度计包括质量，第一组电容，第三组电容与第一组电容相邻。 该物体限定上表面，平行于上表面的下表面和连接上表面和下表面的侧壁。 第一组电容包括第一可移动电极，第三组电容包括第三可移动电极。 第一可动电极垂直于第三可移动电极。

公开(公告)号：US20110241213A1

公开(公告)日：2011-10-06

申请号：US12754912

申请日：2010-04-06

Applicant: Andrew J. Kellock ,  Christian Lavoie ,  Ahmet Ozcan ,  Stephen Rossnagel ,  Bin Yang ,  Zhen Zhang ,  Yu Zhu ,  Stefan Zollner

Inventor： Andrew J. Kellock ,  Christian Lavoie ,  Ahmet Ozcan ,  Stephen Rossnagel ,  Bin Yang ,  Zhen Zhang ,  Yu Zhu ,  Stefan Zollner

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L21/28518 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a silicide contact includes depositing a metal layer on silicon such that the metal layer intermixes with the silicon to form an intermixed region on the silicon; removing an unintermixed portion of the metal layer from the intermixed region; and annealing the intermixed region to form a silicide contact on the silicon. A semiconductor device comprising a silicide contact located over a silicon layer of the semiconductor device, the silicide contact comprising nickel (Ni) and silicon (Si) and having Ni amount equivalent to a thickness of about 21 angstroms or less.

Abstract translation: 形成硅化物接触的方法包括在硅上沉积金属层，使得金属层与硅混合以在硅上形成混合区; 从所述混合区域去除所述金属层的未混合部分; 并且对所述混合区进行退火以在所述硅上形成硅化物接触。 一种半导体器件，包括位于所述半导体器件的硅层上方的硅化物触点，所述硅化物触点包括镍（Ni）和硅（Si），并且具有相当于约21埃或更小的厚度的Ni量。