公开(公告)号：US20170110549A1

公开(公告)日：2017-04-20

申请号：US14887927

申请日：2015-10-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L29/417 ,  H01L27/02 ,  H01L29/06 ,  H01L27/088 ,  H01L29/45 ,  H01L29/08

CPC classification number: H01L29/41775 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative device disclosed herein includes a stepped conductive source/drain structure with a cavity defined therein, the cavity being located vertically above an active region, a non-conductive structure positioned in the cavity, a layer of insulating material positioned above the gate structure, the stepped conductive source/drain structure and the non-conductive structure, a gate contact opening defined in the layer of insulating material and a conductive gate contact positioned in the gate contact opening that is conductively coupled to the gate structure, wherein at least a portion of the conductive gate contact is positioned vertically above the non-conductive structure.

公开(公告)号：US09601387B2

公开(公告)日：2017-03-21

申请号：US14147108

申请日：2014-01-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Harry Cai ,  Chanro Park ,  Hoon Kim

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/823828 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/28176 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/66545

Abstract: Methods of forming a PFET dielectric cap with varying concentrations of H2 reactive gas and the resulting devices are disclosed. Embodiments include forming p-type and n-type metal gate stacks, each surrounded by SiN spacers; forming an ILD surrounding the SiN spacers; planarizing the ILD, the metal gate stacks, and the SiN spacers; determining at least one desired threshold voltage for the p-type metal gate stack; forming a first cavity in the p-type metal gate stack for each desired threshold voltage and a second cavity in the n-type metal gate stack; selecting a first nitride layer for each first cavity, the first nitride layer for each cavity having a concentration of hydrogen reactive gas based on the desired threshold voltage associated with the cavity; forming the first nitride layers in the respective first cavities; and forming a second nitride layer, with a hydrogen rich reactive gas, in the second cavity.

公开(公告)号：US20170040220A1

公开(公告)日：2017-02-09

申请号：US14820701

申请日：2015-08-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Ruilong Xie ,  Min Gyu Sung ,  Chanro Park

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/28 ,  H01L29/49 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L21/82345 ,  H01L21/02181 ,  H01L21/28088 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A method includes forming first and second gate cavities so as to expose first and second portions of a semiconductor material. A gate insulation layer is formed in the first and second gate cavities. A first work function material layer is formed in the first gate cavity. A second work function material layer is formed in the second gate cavity. A first barrier layer is selectively formed above the first work function material layer and the gate insulation layer in the first gate cavity. A second barrier layer is formed above the first barrier layer in the first gate cavity and above the second work function material layer and the gate insulation layer in the second gate cavity. A conductive material is formed above the second barrier layer in the first and second gate cavities in the presence of a treatment species to define first and second gate electrode structures.

Abstract translation: 一种方法包括形成第一和第二栅极腔以暴露半导体材料的第一和第二部分。 栅极绝缘层形成在第一和第二栅极腔中。 第一工作功能材料层形成在第一浇口腔中。 第二工作功能材料层形成在第二浇口腔中。 第一栅极层选择性地形成在第一栅极腔上的第一功函数材料层和栅极绝缘层之上。 第二势垒层形成在第一栅极腔中的第一势垒层上方，并且在第二栅极腔中的第二功函数材料层和栅极绝缘层之上。 在存在处理物质的情况下，在第一和第二栅极腔中的第二阻挡层上方形成导电材料，以限定第一和第二栅电极结构。

公开(公告)号：US09508604B1

公开(公告)日：2016-11-29

申请号：US15142052

申请日：2016-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/3115

CPC classification number: H01L21/823821 ,  H01L27/0924 ,  H01L29/6656 ,  H01L29/66803 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a first plurality of fins for a type 1 device and a second plurality of fins for a type 2 device, forming a first counter-doped sidewall spacer structure adjacent the first fins, forming a second counter-doped sidewall spacer structure adjacent the second fins and a counter-doped material structure in a space between the first fins, forming a recessed layer of flowable oxide on the devices such that portions of the first and second counter-doped sidewall spacers are exposed above the flowable oxide layer, and performing a common etching process operation to remove at least a portion of the exposed portions of the first and second counter-doped sidewall spacer structures.

Abstract translation: 本文公开的一种说明性方法包括形成用于类型1装置的第一多个翅片和用于2型装置的第二多个翅片，形成与第一翅片相邻的第一反掺杂侧壁间隔结构，形成 邻近第二散热片的第二反掺杂侧壁间隔结构和在第一散热片之间的空间中的反掺杂材料结构，在器件上形成可流动氧化物的凹陷层，使得第一和第二反掺杂侧壁间隔物的部分为 暴露在可流动氧化物层之上，并执行公共蚀刻工艺操作以去除第一和第二反掺杂侧壁间隔结构的暴露部分的至少一部分。

公开(公告)号：US09502308B1

公开(公告)日：2016-11-22

申请号：US14944659

申请日：2015-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Hoon Kim ,  Ruilong Xie ,  Min Gyu Sung

IPC: H01L21/70 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/092 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L21/823871 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924

Abstract: A method includes forming first and second contact openings so as to expose first and second source/drain regions, respectively, of a semiconductor material. At least one process operation is performed to selectively form a first liner only in the first contact opening. The first liner covers a bottom portion of the first contact opening and exposes a sidewall portion of the first contact opening. A second liner is formed in the first and second contact openings. At least one process operation is performed so as to form a conductive material above the second liner to fill the first and second contact openings and define first and second contacts conductively coupled to the first and second source/drain regions, respectively.

Abstract translation: 一种方法包括形成第一和第二接触开口以分别暴露半导体材料的第一和第二源/漏区。 执行至少一个处理操作以仅在第一接触开口中选择性地形成第一衬里。 第一衬垫覆盖第一接触开口的底部并暴露第一接触开口的侧壁部分。 第二衬垫形成在第一和第二接触开口中。 执行至少一个处理操作，以在第二衬垫上方形成导电材料，以填充第一和第二接触开口，并分别限定导电耦合到第一和第二源/漏区的第一和第二触点。

公开(公告)号：US09478661B1

公开(公告)日：2016-10-25

申请号：US14696954

申请日：2015-04-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Hoon Kim ,  Min Gyu Sung

IPC: H01L21/308 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L29/785 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/66795

Abstract: Semiconductor device structures having fin structure(s) and fabrication methods thereof are presented. The methods include: providing a first mask above a substrate structure and a second mask above the first mask and the substrate structure; removing portions of the first mask not underlying the second mask and selectively etching the substrate structure using the second mask to form at least one cavity therein; providing a third mask over portions of the substrate structure not underlying the second mask and removing the second mask; and selectively etching the substrate structure using remaining portions of the first mask and the third mask to the form fin structure(s) of the semiconductor device structure, where the fin structure(s) is self-aligned with the at least one cavity in the substrate structure. For example, the semiconductor device structure can be a fin-type transistor structure, and the method can include forming a source/drain region within a cavity.

Abstract translation: 提出了具有翅片结构的半导体器件结构及其制造方法。 所述方法包括：在第一掩模和衬底结构之上提供衬底结构上方的第一掩模和第二掩模; 去除第一掩模的不在第二掩模下面的部分，并使用第二掩模选择性地蚀刻衬底结构，以在其中形成至少一个空腔; 在不在所述第二掩模下方的所述衬底结构的部分上提供第三掩模并且移除所述第二掩模; 以及使用所述第一掩模和所述第三掩模的剩余部分将所述衬底结构选择性地蚀刻到所述半导体器件结构的形式鳍结构，其中所述鳍结构与所述第一掩模和所述第三掩模中的所述至少一个空腔自对准 底物结构。 例如，半导体器件结构可以是鳍式晶体管结构，并且该方法可以包括在腔内形成源极/漏极区域。

公开(公告)号：US20160181426A1

公开(公告)日：2016-06-23

申请号：US15055805

申请日：2016-02-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hoon Kim ,  Chanro Park ,  Min Gyu Sung

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/165 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: A device includes a gate structure having an axial length that is positioned above an active region of a semiconductor substrate and includes a first gate structure portion positioned above the active region and second gate structure portions positioned above an isolation region formed in the semiconductor substrate. An etch stop layer is positioned on the gate structure and covers sidewall surfaces of the second gate structure portions but does not cover any sidewall surfaces of the first gate structure portion. First and second contact trenches extend continuously along the first gate structure portion for less than the axial length of the gate structure and are positioned above at least a portion of the active region on respective opposing first and second sides of the gate structure. An epi semiconductor material is positioned on the active region within each of the first and second contact trenches.

Abstract translation: 一种器件包括具有位于半导体衬底的有源区上方的轴向长度的栅极结构，并且包括位于有源区上方的第一栅极结构部分和位于半导体衬底中形成的隔离区上方的第二栅极结构部分。 蚀刻停止层位于栅极结构上并且覆盖第二栅极结构部分的侧壁表面，但不覆盖第一栅极结构部分的任何侧壁表面。 第一和第二接触沟槽沿着第一栅极结构部分连续延伸以小于栅极结构的轴向长度，并且位于栅极结构的相对的相对的第一和第二侧上的有源区域的至少一部分上方。 外延半导体材料位于第一和第二接触沟槽的每一个内的有源区域上。

公开(公告)号：US20160042954A1

公开(公告)日：2016-02-11

申请号：US14452606

申请日：2014-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim

IPC: H01L21/28 ,  H01L29/49 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/28123 ,  H01L21/28088 ,  H01L21/32139 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Embodiments of the present invention provide a replacement metal gate and a fabrication process with reduced lithography steps. Using selective etching techniques, a layer of fill metal is used to protect the dielectric layer in the trenches, eliminating the need for some lithography steps. This, in turn, reduces the overall cost and complexity of fabrication. Furthermore, additional protection is provided during etching, which serves to improve product yield.

Abstract translation: 本发明的实施例提供了一种替代金属栅极和具有减小的光刻步骤的制造工艺。 使用选择性蚀刻技术，使用一层填充金属来保护沟槽中的电介质层，消除了对一些光刻步骤的需要。 这又降低了整体成本和制造的复杂性。 此外，在蚀刻期间提供额外的保护，其用于提高产品产率。

公开(公告)号：US09178036B1

公开(公告)日：2015-11-03

申请号：US14492629

申请日：2014-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Naim Moumen ,  Chanro Park ,  Hoon Kim ,  Steven Bentley

IPC: H01L21/336 ,  H01L27/092 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L27/092 ,  H01L21/28 ,  H01L21/28114 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545

Abstract: One illustrative method disclosed herein includes, among other things, performing at least one recess etching process such that a first portion of a high-k oxide gate insulation layer and a first portion of a metal oxide layer is positioned entirely within a first gate cavity and a second portion of the high-k oxide gate insulation layer, a conformal patterned masking layer and a second portion of the metal oxide layer is positioned entirely within a second gate cavity, performing at least one heating process to form a composite metal-high-k oxide alloy gate insulation layer in the first gate cavity, while preventing metal from the metal oxide material from being driven into the second portion of the high-k oxide gate insulation layer in the second gate cavity during the at least one heating process, and forming gate electrode structures in the gate cavities.

Abstract translation: 本文公开的一种说明性方法包括进行至少一个凹陷蚀刻工艺，使得高k氧化物栅极绝缘层的第一部分和金属氧化物层的第一部分完全位于第一栅极腔内， 高k氧化物栅极绝缘层的第二部分，共形图案化掩模层和金属氧化物层的第二部分完全位于第二栅极腔内，执行至少一个加热工艺以形成复合金属 - k氧化物合金栅极绝缘层，同时防止来自金属氧化物材料的金属在至少一个加热过程中被驱入第二栅极腔中的高k氧化物栅极绝缘层的第二部分，以及 在门腔中形成栅电极结构。

公开(公告)号：US09140975B2

公开(公告)日：2015-09-22

申请号：US14106219

申请日：2013-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Sun ,  Chanro Park ,  Wenhui Wang ,  Hui Zang

IPC: G03F1/62 ,  G03F1/64 ,  G03F1/00 ,  G03F1/22

CPC classification number: G03F1/142 ,  G03F1/22 ,  G03F1/62 ,  G03F1/64

Abstract: A method of forming an improved EUV mask and pellicle with airflow between the area enclosed by the mask and pellicle and the area outside the mask and pellicle and the resulting device are disclosed. Embodiments include forming a frame around a patterned area on an EUV mask; forming a membrane over the frame; and forming holes in the frame.

Abstract translation: 公开了一种在由掩模和防护薄膜组成的区域与掩模和防护薄膜之间的区域以及所得到的装置之间形成改进的EUV掩模和防护薄膜组件的方法。 实施例包括在EUV掩模上的图案化区域周围形成框架; 在框架上形成膜; 并在框架中形成孔。