公开(公告)号：US20240251555A1

公开(公告)日：2024-07-25

申请号：US18585372

申请日：2024-02-23

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Jordan D. Greenlee

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions. Channel-material-pillars are arranged within the memory regions. Conductive posts are arranged within the intermediate region. A panel extends across the memory regions and the intermediate region. The panel is laterally between a first memory-block-region and a second memory-block-region. Doped-semiconductor-material is within the memory regions and the intermediate region, and is directly adjacent to the panel. The doped-semiconductor-material is at least part of conductive source structures within the memory regions. Insulative rings laterally surround lower regions of the conductive posts and are between the conductive posts and the doped-semiconductor-material. Insulative liners are along upper regions of the conductive posts. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240081070A1

公开(公告)日：2024-03-07

申请号：US17929965

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Jordan D. Greenlee

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11582

Abstract: Source terminals of memory devices and related apparatuses, computing systems, and methods are disclosed. An apparatus includes a first polysilicon material, a second polysilicon material offset from the first polysilicon material, an intervening polysilicon material between the first polysilicon material and the second polysilicon material, and pillars defining memory cells. The pillars extend through the second polysilicon material and a proximal portion of the intervening polysilicon material into the first polysilicon material. The one or more insulative materials are at a distal edge of the intervening polysilicon material. The intervening polysilicon material is thicker at the distal edge than at the pillars. A method includes removing, using an isotropic etch process, portions of the first polysilicon material and the second polysilicon material in a trench and forming the intervening polysilicon material between the first polysilicon material and the second polysilicon material.

公开(公告)号：US20240071816A1

公开(公告)日：2024-02-29

申请号：US17896919

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  Lifang Xu ,  Jordan D. Greenlee

IPC: H01L21/768 ,  H01L23/535 ,  H01L27/11526 ,  H01L27/11573

CPC classification number: H01L21/76816 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76895 ,  H01L23/535 ,  H01L27/11526 ,  H01L27/11573

Abstract: Methods, systems, and devices for staircase formation in a memory array are described. A liner composed of a first liner material may be deposited on a tread and a first portion of the liner may be doped. After doping the first portion of the liner, a second portion of the liner may be converted into a second liner material using a chemical process. After converting the second portion of the liner into the second liner material, the first portion of the liner material may be removed so that a subsequent removal process can expose a first sub-tread. After exposing the first sub-tread, the second portion of the liner may be removed so that a second sub-tread is exposed.

公开(公告)号：US20240071495A1

公开(公告)日：2024-02-29

申请号：US17896775

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Jiewei Chen ,  Jordan D. Greenlee ,  Shuangqiang Luo ,  Silvia Borsari

IPC: G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs having insulative material atop treads of the stairs. Individual of the treads comprise conducting material of one of the conductive tiers. Conductive vias extend through the insulative material. Individual of the conductive vias are directly above and directly against the conducting material of the respective individual tread. A lining is over sidewalls of the individual conductive vias. The lining has a bottom. The individual conductive vias are directly under the bottom of the lining directly above the conducting material of the respective individual tread. Other embodiments, including method, are disclosed.

公开(公告)号：US11910596B2

公开(公告)日：2024-02-20

申请号：US17223254

申请日：2021-04-06

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Alyssa N. Scarbrough ,  John D. Hopkins

IPC: H10B41/27 ,  G11C5/06 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/06 ,  H10B43/27

Abstract: Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and said other region, and separates a first memory-block-region from a second memory-block-region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. Rings laterally surround lower regions of the conductive posts. The rings are between the conductive posts and the doped-semiconductor-material. The rings include laminates of two or more materials, with at least one of said two or more materials being insulative. Some embodiments include methods for forming integrated assemblies.

公开(公告)号：US11895834B2

公开(公告)日：2024-02-06

申请号：US17674478

申请日：2022-02-17

Applicant: Micron Technology, Inc.

Inventor： Jiewei Chen ,  Jordan D. Greenlee ,  Mithun Kumar Ramasahayam ,  Nancy M. Lomeli

IPC: H10B41/10 ,  G11C16/04 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B41/10 ,  G11C16/0483 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B41/35 ,  H10B43/35

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are between immediately-laterally-adjacent of the memory blocks. Conductor material is in and extends elevationally along sidewalls of the trenches laterally-over the conductive tiers and the insulative tiers and directly electrically couples together conducting material of individual of the conductive tiers. The conductor material is exposed to oxidizing conditions to form an insulative oxide laterally-through the conductor material laterally-over individual of the insulative tiers to separate the conducting material of the individual conductive tiers from being directly electrically coupled together by the conductor material. Additional embodiments are disclosed.

公开(公告)号：US20240032295A1

公开(公告)日：2024-01-25

申请号：US17813847

申请日：2022-07-20

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee

IPC: H01L27/11582 ,  H01L27/11543 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L27/11543 ,  H01L29/40117

Abstract: Electronic devices comprising a source stack comprising one or more conductive materials, a source contact adjacent to the source stack, tiers of alternating conductive materials and insulative materials adjacent to the source contact, pillars extending through the tiers and the source contact and into the source stack, a slit structure extending through the tiers and the source contact, and an implant structure extending within the slit structure and into the source stack. Related methods and systems are also disclosed.

公开(公告)号：US20230395510A1

公开(公告)日：2023-12-07

申请号：US17812141

申请日：2022-07-12

Applicant: Micron Technology, Inc.

Inventor： Mithun Kumar Ramasahayam ,  Jordan D. Greenlee ,  Harsh Narendrakumar Jain ,  Jiewei Chen ,  Indra V. Chary

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53242 ,  H01L23/53257 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76888

Abstract: Microelectronic devices include a stack with a vertically alternating sequence of insulative and conductive structures arranged in tiers. A staircased stadium within the stack comprises steps at different tier elevations of a group of the tiers. Treads of the steps are each provided by an upper surface area of one of the conductive structures within the group of the tiers and by an upper surface area of a metal oxide region extending through the one of the conductive structures. A pair of conductive contact structures extends to one of the steps. A first conductive contact structure of the pair terminates at the tread of the step, within the area of the conductive structure. A second conductive contact structure of the pair extends through the tread of the step, within the upper surface area of the metal oxide region. Related fabrication methods and electronic systems are also disclosed.

公开(公告)号：US20230389313A1

公开(公告)日：2023-11-30

申请号：US17869586

申请日：2022-07-20

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Jiewei Chen ,  John D. Hopkins ,  Everett A. McTeer

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a first vertical stack comprising vertically-alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. A second vertical stack is aside the first vertical stack. The second vertical stack comprises insulative tiers collectively comprising at least two different compositions relative individual of the insulative tiers. Individual of the at least two different compositions comprise silicon nitride. One of the individual different compositions comprise carbon-doped silicon nitride having at least 0.5 atomic percent more carbon than atomic percent of carbon, if any, in the silicon nitride of another of the individual different compositions. Other embodiments, including method, are disclosed.

公开(公告)号：US20230380172A1

公开(公告)日：2023-11-23

申请号：US17748924

申请日：2022-05-19

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Jordan D. Greenlee ,  Daniel Billingsley ,  Alyssa N. Scarbrough

IPC: H01L27/11573 ,  H01L27/11529

CPC classification number: H01L27/11573 ,  H01L27/11529

Abstract: Methods, systems, and devices for a barrier structure for preventing removal of, such as etching to, control circuitry are described. A memory device may include control circuitry over a substrate and for accessing a memory array and contact regions configured to couple with the control circuitry. The memory device may include barrier regions between respective contact regions that includes a barrier material. The memory device may include a stack of layers over the barrier region and the contact regions that is associated with the memory array, and the barrier material may prevent a removal (e.g., an etch) through the stack of layers and at least partially between contact regions from extending to the control circuitry.