公开(公告)号：US20150293557A1

公开(公告)日：2015-10-15

申请号：US14751312

申请日：2015-06-26

Applicant: RAMBUS INC.

Inventor： Scott C. Best ,  Abhijit M. Abhyankar ,  Kun-Yung Chang ,  Frank Lambrecht

IPC: G06F1/08 ,  G06F1/12

CPC classification number: G06F1/08 ,  G06F1/12 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/14

Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.

Abstract translation: 一种存储器控制器，具有数据接收器，用于使用选通信号在采样定时采样数据，其中所述数据和所述选通信号由存储器件发送，与由所述存储器控制器发起的读取操作相结合;以及选通接收器，用于接收 所述选通信号，其中所述选通信号的相位相对于参考具有相对于所述量的漂移。 存储器控制器还具有监控电路以监视选通信号并确定漂移量;以及调整电路，用于基于由监视信号确定的漂移量来更新数据接收器的采样定时。

公开(公告)号：US20150248327A1

公开(公告)日：2015-09-03

申请号：US14631570

申请日：2015-02-25

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent S. Haukness ,  John Eric Linstadt ,  Scott C. Best

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1048 ,  G11C5/04 ,  G11C29/42 ,  G11C29/44 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

Abstract translation: 公开了一种存储器模块。 存储器模块包括衬底以及相应的第一，第二和第三存储器件。 第一存储器件是第一类型，其设置在衬底上并且具有可寻址的存储位置。 第二存储器件也是第一类型，并且包括专用于存储与第一存储器件中的不良存储位置相关联的故障地址信息的存储单元。 第三存储器件是第一类型的，并且包括专用于替换为存储位置不良的存储单元的存储单元。

公开(公告)号：US20150138895A1

公开(公告)日：2015-05-21

申请号：US14578078

申请日：2014-12-19

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G11C11/4093 ,  G11C11/408

CPC classification number: G11C11/4082 ,  G06F12/06 ,  G06F13/1673 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

Abstract translation: 本文描述的实施例描述了在不同操作模式下使用存储器模块的技术，例如在标准多点模式或动态点对点（DPP）模式（此处也称为增强模式）中， 。 内存模块也可以以不同的配置插入存储系统的插座。

公开(公告)号：US20150103943A1

公开(公告)日：2015-04-16

申请号：US14573773

申请日：2014-12-17

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  John W. Poulton

IPC: H04L25/08 ,  G11C5/14 ,  H04L1/20

CPC classification number: G11C5/144 ,  G06F11/0727 ,  G06F11/076 ,  G06F11/0793 ,  G06F13/4072 ,  G11C5/145 ,  H04L1/203 ,  H04L25/0264 ,  H04L25/08

Abstract: In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.

Abstract translation: 在数据传输系统中，在第一电路中生成用于产生要发送的信号的信令电压的一个或多个信号电源电压，并从第一电路转发到第二电路。 第二电路可以使用转发的信号电源电压来产生要从第二电路传输回第一电路的另一个信号，从而避免在第二电路中单独产生信号电源电压的需要。 第一电路还可以基于从第二电路传输回第一电路的信号来调整信号电源电压。 数据传输系统可以使用单端信令系统，其中信令电压参考作为由第一电路和第二电路共享的诸如地的电源电压的参考电压。

公开(公告)号：US20150033044A1

公开(公告)日：2015-01-29

申请号：US14452373

申请日：2014-08-05

Applicant: Rambus Inc.

Inventor： Ely Tsern ,  Thomas Vogelsang ,  Craig Hampel ,  Scott C. Best

IPC: G06F3/06 ,  G06F1/26 ,  G11C5/14

CPC classification number: G06F3/0625 ,  G06F1/266 ,  G06F3/0634 ,  G06F3/0673 ,  G11C5/147 ,  G11C11/4074 ,  G11C2207/2227

Abstract: A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes.

Abstract translation: 内存系统支持高性能和低功耗模式。 存储器系统包括存储器核和核心接口。 存储器内核采用在两种模式下保持相同的核心电源电压。 核心接口的电源电压和信号速率可以缩小以节省功耗。 存储器核心和核心接口电平之间的电平移位器根据需要移位信号以适应不同模式下核心接口所使用的信令电压。

公开(公告)号：US20140153310A1

公开(公告)日：2014-06-05

申请号：US14091213

申请日：2013-11-26

Applicant: Rambus Inc.

Inventor： Deepak Chandra Sekar ,  Brent Steven Haukness ,  John Eric Linstadt ,  Scott C. Best

IPC: G11C15/00 ,  G11C13/00

CPC classification number: G11C15/00 ,  G11C13/0002 ,  G11C15/046

Abstract: A content addressable memory can include an array of memory cells having multiple memory elements, such as RRAM elements, to store data based on a plurality resistive states. A common switching device, such as a transistor, can electrically couple a plurality of the multiple memory elements with a matchline during read, write, erase, and search operations. In search operations, the memory cells can receive a search word and selectively discharge a voltage level on the matchline based on the data stored by the memory elements and the search word provided to the memory elements. The voltage level of the matchline can indicate whether the search word matched the data stored in the memory cells. The content addressable memory can potentially have an effective memory cell sizing under 0.5F2 depending on the number of layers of memory cells formed over the switching device.

Abstract translation: 内容可寻址存储器可以包括具有多个存储器元件（诸如RRAM元件）的存储器单元阵列，以存储基于多个电阻状态的数据。 诸如晶体管的公共开关器件可以在读，写，擦除和搜索操作期间用匹配线电耦合多个多个存储器元件。 在搜索操作中，存储器单元可以接收搜索词，并且基于由存储元件存储的数据和提供给存储器元件的搜索词来选择性地排放匹配线上的电压电平。 匹配线的电压电平可以指示搜索词是否匹配存储在存储单元中的数据。 内容可寻址存储器可能潜在地具有根据在开关器件上形成的存储器单元的层数在0.5F2下的有效存储单元大小。

公开(公告)号：US08666007B2

公开(公告)日：2014-03-04

申请号：US13687391

申请日：2012-11-28

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Richard E. Warmke ,  David B. Roberts ,  Frank Lambrecht

IPC: H04L7/00

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4091 ,  G11C2207/107 ,  H03L7/07 ,  H03L7/0814 ,  H04L7/0337

Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.

Abstract translation: 存储器控制器从存储器件接收数据和相位提供信号。 相位提供信号不是时钟信号，而是被存储器控制器用来将本地数据采样信号与输入数据进行相位调整。 存储器控制器用数据采样信号对数据信号进行采样。 存储器控制器可以执行维护操作以更新相位提供和数据采样信号之间的相位关系。