公开(公告)号：US11894073B2

公开(公告)日：2024-02-06

申请号：US17487665

申请日：2021-09-28

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/24 ,  G11C16/08 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/3431 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines including at least one edge word line and a plurality of other data word lines. The memory cells are arranged in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. The memory apparatus also includes a control means coupled to the plurality of word lines and the strings. The control means is configured to identify the at least one edge word line. The control means is also configured to periodically apply a program voltage to the at least one edge word line to reprogram the memory cells associated with the at least one edge word line without erasing the memory cells associated with the at least one edge word line.

公开(公告)号：US11894072B2

公开(公告)日：2024-02-06

申请号：US17724769

申请日：2022-04-20

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Xiang Yang ,  Abhijith Prakash

IPC: G11C16/08 ,  G11C16/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/3427 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3459

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in strings. A control means is coupled to the word lines and the strings and is configured to ramp a voltage applied to a selected one of the word lines from a verify voltage to a reduced voltage during a program-verify portion of a program operation. The control means successively ramps voltages applied to each of a plurality of neighboring ones of the word lines from a read pass voltage to the reduced voltage beginning with ones of the plurality of neighboring ones of the word lines immediately adjacent the selected one of the word lines and progressing to ones of the plurality of neighboring others of the word lines disposed increasingly remotely from the selected one of the word lines during the program-verify portion of the program operation.

公开(公告)号：US20240029789A1

公开(公告)日：2024-01-25

申请号：US17870055

申请日：2022-07-21

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta

IPC: G11C11/56 ,  G11C16/10 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: G11C11/5671 ,  G11C11/5628 ,  G11C16/10 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: The memory die that includes a plurality of memory blocks. Each memory block includes a plurality of memory cells that are configured to store three bits of data in each memory cell when the memory die is in a TLC operating mode. The memory die has a non-binary data capacity, which is a multiple of 683 Gb, when the memory die is operating in the TLC operating mode.

公开(公告)号：US11871580B2

公开(公告)日：2024-01-09

申请号：US17317479

申请日：2021-05-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peng Zhang ,  Yanli Zhang ,  Xiang Yang ,  Koichi Matsuno ,  Masaaki Higashitani ,  Johann Alsmeier

IPC: H10B51/30 ,  H01L21/764 ,  H01L29/06 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B51/20

CPC classification number: H10B51/30 ,  H01L21/764 ,  H01L29/0649 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B51/20

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.

公开(公告)号：US20230410906A1

公开(公告)日：2023-12-21

申请号：US17824143

申请日：2022-05-25

Applicant: SanDisk Technologies LLC

Inventor： Yi Song ,  Jiahui Yuan ,  Xiang Yang

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/28 ,  G11C16/10

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/28 ,  G11C16/08

Abstract: An apparatus includes a control circuit configured to connect to memory cells connected in series in NAND strings. Each NAND string includes a plurality of data memory cells coupled to a plurality of data word lines in series with a plurality of dummy memory cells connected to a plurality of dummy word lines. The control circuit configured to apply a first dummy word line voltage to one or more dummy word lines of the plurality of dummy word lines in a verify step of a program operation to program data memory cells. The control circuit is configured to apply a second dummy word line voltage to the one or more dummy word lines in a read operation to read the data memory cells.

公开(公告)号：US11699495B2

公开(公告)日：2023-07-11

申请号：US17349118

申请日：2021-06-16

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang

IPC: G11C16/00 ,  G11C16/34 ,  G11C16/26 ,  G11C16/14 ,  G11C16/10

CPC classification number: G11C16/3495 ,  G11C16/102 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3463

Abstract: A method for programming a memory block of a non-volatile memory structure, comprising determining whether a number of programming/erase cycles previously applied to the block exceeds a first programming/erase cycle threshold and, if the first threshold is exceeded, determining whether the number of programming/erase cycles previously applied to the block exceeds an extended programming/erase cycle threshold. Further, if the determination is made that the extended threshold is not exceeded, the method comprises applying a two-pulse per programming loop scheme to each of the outermost strings of the block and applying a single-pulse per programming loop scheme to all other strings of the block. Alternatively, or in addition thereto, relative to a programming/erase cycle threshold, one or more outermost strings of the block may be unpermitted to be further programmed, and a “sub-block” comprised of all valid strings of the block may be defined and permitted for further programming.

公开(公告)号：US20230207021A1

公开(公告)日：2023-06-29

申请号：US17561016

申请日：2021-12-23

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Xiang Yang

IPC: G11C16/16 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/16 ,  G11C16/105 ,  G11C16/26

Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to word lines and disposed in memory holes. The memory cells are connected in series between a drain-side select gate transistor on a drain-side and connected to one of a plurality of bit lines and a source line on a source-side. A control means is configured to apply a first and a second select gate voltage to the drain-side select gate transistor while applying a predetermined source line voltage to the source line of selected ones of the memory holes in a predetermined grouping and a read level voltage to at least one of the word lines associated with the predetermined grouping. The control means counts the memory cells conducting during each of a first and a second read operation and adjusts the predetermined source line voltage accordingly.

公开(公告)号：US11646081B2

公开(公告)日：2023-05-09

申请号：US17392500

申请日：2021-08-03

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Peter Rabkin ,  Henry Chin ,  Ken Oowada ,  Dengtao Zhao ,  Gerrit Jan Hemink

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C11/56 ,  H01L27/11565 ,  H01L25/065 ,  H01L27/11582

CPC classification number: G11C16/10 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/349 ,  H01L25/0657 ,  H01L27/11565 ,  H01L27/11582 ,  H01L2225/06562

Abstract: Technology is provided for extending the useful life of a block of memory cells by changing an operating parameter in a physical region of the block that is more susceptible to wear than other regions. Changing the operating parameter in the physical region extends the life of that region, which extends the life of the block. The operating parameter may be, for example, a program voltage step size or a storage capacity of the memory cells. For example, using a smaller program voltage step size in a sub-block that is more susceptible to wear extends the life of that sub-block, which extends the life of the block. For example, programming memory cells to fewer bits per cell in the region of the block (e.g., sub-block, word line) that is more susceptible to wear extends the useful life of that region, which extends the life of the block.

公开(公告)号：US20230131500A1

公开(公告)日：2023-04-27

申请号：US17509725

申请日：2021-10-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Arka Ganguly ,  Ohwon Kwon

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4074 ,  G06F3/06

Abstract: An apparatus includes a control circuit and a plurality of non-volatile memory cells arranged in a plane of a memory die. The plane includes a first word line including a first word line portion coupled to a corresponding first group of the non-volatile memory cells, and a second word line including a second word line portion coupled to a corresponding second group of the non-volatile memory cells, the second word line different from the first word line. The control circuit is configured to apply a first voltage to the first word line portion and apply a second voltage to the second word line portion to concurrently read the first group of the non-volatile memory cells and the second group of the non-volatile memory cells. The first group of the non-volatile memory cells and the second group of the non-volatile memory cells each store less than a page of data.

公开(公告)号：US20230130394A1

公开(公告)日：2023-04-27

申请号：US17511818

申请日：2021-10-27

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Abhijith Prakash ,  Shubhajit Mukherjee

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04 ,  G11C16/24

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines including at least one edge word line and other data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage corresponding to data states. The strings are organized in rows and a control means is coupled to the word lines and the strings and identifies the at least one edge word line. The control means programs the memory cells of the strings in particular ones of the rows and associated with the at least one edge word line to have an altered distribution of the threshold voltage for one or more of the data states compared to the memory cells of the strings not in particular ones of the rows and not associated with the at least one edge word line during a program operation.