公开(公告)号：US10366915B2

公开(公告)日：2019-07-30

申请号：US15847307

申请日：2017-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/764 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes a first gate structure disposed over a substrate. The first gate structure extends in a first direction. A second gate structure is disposed over the substrate. The second gate structure extends in the first direction. A dielectric material is disposed between the first gate structure and the second gate structure. An air gap is disposed within the dielectric material.

公开(公告)号：US20190148520A1

公开(公告)日：2019-05-16

申请号：US15885036

申请日：2018-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Wei-Chiang Hung ,  Wei-Hao Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/417 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02667 ,  H01L21/30625 ,  H01L21/3086 ,  H01L21/324 ,  H01L21/76224 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7848 ,  H01L29/785

Abstract: Examples of an integrated circuit and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a substrate that includes: a plurality of fins extending above a remainder of the substrate; a first region that includes a first fence region that contains a first subset of the plurality of fins; and a second region that includes a second fence region that contains a second subset of the plurality of fins. The first region has a first performance characteristic, and the second region has a second performance characteristic that is different from the first. Based on the first performance characteristic, the first subset of the plurality of fins is recessed to a first height, and based on the second performance characteristic, the second subset of the plurality of fins is recessed to a second height that is less than the first height.

公开(公告)号：US10276662B2

公开(公告)日：2019-04-30

申请号：US15168323

申请日：2016-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Han Lin

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/08 ,  H01L23/525 ,  H01L23/528 ,  H01L23/535 ,  H01L29/78 ,  H01L27/092 ,  H01L27/11521 ,  H01L29/423

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first gate stack and a second gate stack over a substrate. Each of them has gate spacers disposed along its respective sidewalls. The method also includes forming a source/drain (S/D) feature disposed between the first and second gate stacks. The gate spacers and a top surface of the S/D feature define a space. The method also includes forming a first dielectric layer over the S/D feature in the space, forming a capping layer along the gate spacers in the space, forming a second dielectric layer over the first dielectric layer in the space and forming a contact trench extending through the second dielectric layer, the first dielectric layer and the capping layer to expose the top surface of the S/D feature.

公开(公告)号：US20190109235A1

公开(公告)日：2019-04-11

申请号：US16214156

申请日：2018-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin-type field effect transistor comprising a substrate, a plurality of insulators, at least one gate stack and strained material portions is described. The substrate has a plurality of fins thereon and the fin comprises a stop layer embedded therein. The plurality of insulators is disposed on the substrate and between the plurality of fins. The at least one gate stack is disposed over the plurality of fins and on the plurality of insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.

公开(公告)号：US10163649B2

公开(公告)日：2018-12-25

申请号：US15048942

申请日：2016-02-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L23/535 ,  H01L21/311 ,  H01L27/088 ,  H01L27/02 ,  H01L29/08 ,  H01L21/768

Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, at least one conductive plug, and at least one protection layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure. The protection layer is present between the conductive plug and the spacer.

公开(公告)号：US20180350821A1

公开(公告)日：2018-12-06

申请号：US16046369

申请日：2018-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Han Lin ,  Che-Cheng Chang ,  Horng-Huei Tseng

IPC: H01L27/11 ,  H01L49/02 ,  H01L27/11582 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3065 ,  H01L29/165

Abstract: A method of forming a semiconductor device includes receiving a substrate with a plurality of gate structures; forming spacers on sidewalls of the gate structures; evaluating a pitch variation to the gate structures; determining an etch recipe according to the pitch variation; performing an etch process to source/drain regions associated with the gate structures using the etch recipe, thereby forming source/drain recesses with respective depths; and performing an epitaxy growth to form source/drain features in the source/drain recesses using a semiconductor material.

公开(公告)号：US10121787B2

公开(公告)日：2018-11-06

申请号：US15706760

申请日：2017-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/82 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66

Abstract: Method for fabricating Fin field effect transistors (FinFETs) are disclosed. One of the methods includes the following steps. A first semiconductor fin, a second semiconductor fin and an insulator between the first semiconductor fin and the second semiconductor fin are formed. A first dummy gate, a second dummy gate and an opening between the first and second dummy gates are formed over the insulator, wherein the first dummy gate and the second dummy gate cross over portions of the first semiconductor fin and the second semiconductor fin respectively. A dielectric layer is formed in the opening, wherein the dielectric layer comprises an air gap therein. The first dummy gate and the second dummy gate are replaced with a first gate and a second gate, wherein the first gate and the second gate are electrically insulated by the dielectric layer comprising the air gap therein.

公开(公告)号：US10096712B2

公开(公告)日：2018-10-09

申请号：US15002287

申请日：2016-01-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/82 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/66 ,  H01L21/8234 ,  H01L21/67 ,  G01N21/88

Abstract: A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The method includes the steps of: forming a plurality of fins supported by a substrate; depositing a gate layer on the fins; and etching the gate layer by plasma etching with an etching gas to form a gate having two notch features. The etching gas is supplied at a ratio of a flow rate at a center area of the substrate to a flow rate at a periphery area of the substrate in a range from 0.2 to 1. The disclosure also provides a method of monitoring a quality of the FinFET device, the method comprising: measuring a profile of the notch feature; and obtaining the quality of the FinFET device by comparing the profile of the notch feature with a predetermined criterion.

公开(公告)号：US10032914B2

公开(公告)日：2018-07-24

申请号：US14887873

申请日：2015-10-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, an insulating structure, and a gate stack. The substrate has at least one semiconductor fin. The insulating structure is disposed above the substrate and separated from the semiconductor fin to form a gap therebetween. The insulating structure has a sidewall facing the semiconductor fin. The gate stack covers at least a portion of the semiconductor fin and is at least disposed in the gap between the insulating structure and the semiconductor fin. The gate stack includes a high-κ dielectric layer and a gate electrode. The high-κ dielectric layer covers the semiconductor fin while leaves the sidewall of the insulating structure uncovered. The gate electrode is disposed above the high-κ dielectric layer and at least in the gap between the insulating structure and the semiconductor fin.

公开(公告)号：US20180174956A1

公开(公告)日：2018-06-21

申请号：US15891394

申请日：2018-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/02 ,  H01L29/06 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76883 ,  H01L23/53295 ,  H01L29/0649 ,  H01L2221/1031

Abstract: A method for manufacturing an interconnect structure is provided, and the method is as below. A dielectric layer is deposited over a substrate. The dielectric layer is etched to form a recess. A dummy adhesion layer is deposited on sidewalls of the recess. A conductive layer is formed in the recess. The dummy adhesion layer is removed to expose a portion of the conductive layer.