公开(公告)号：US09130789B2

公开(公告)日：2015-09-08

申请号：US13560947

申请日：2012-07-27

Applicant: Karthik Muralidhar ,  George A. Vlantis

Inventor： Karthik Muralidhar ,  George A. Vlantis

IPC: H04B1/40 ,  H04L25/02 ,  H04L25/03 ,  H04L27/26 ,  H04L5/00

CPC classification number: H04L25/022 ,  H04L5/0023 ,  H04L5/0048 ,  H04L25/0204 ,  H04L25/0224 ,  H04L25/03821 ,  H04L27/2601

Abstract: An embodiment of a receiver includes a channel estimator and a data-recovery unit. The channel estimator is configured to determine a characteristic of a channel over which a first signal, which is received simultaneously with a second signal, propagated, the first and second signals respectively having first and second components that include approximately a frequency. And the data-recovery unit is configured to recover data from the first signal in response to the determined channel characteristic. For example, such a receiver may be able to receive simultaneously, and over the same channel space, orthogonal-frequency-division-multiplexed (OFDM) signals that include one or more of the same subcarrier frequencies, and to recover data from one or more of the OFDM signals despite the frequency overlap. A receiver with this capability may allow an increase in the effective bandwidth of the channel space, and thus may allow more devices to simultaneously share the channel space.

Abstract translation: 接收机的实施例包括信道估计器和数据恢复单元。 信道估计器被配置为确定与第二信号同时接收的第一信号传播的信道的特性，第一和第二信号分别具有包括大致频率的第一和第二分量。 并且数据恢复单元被配置为响应于确定的信道特性从第一信号中恢复数据。 例如，这样的接收机可能能够同时并且在同一信道空间上接收包括相同子载波频率中的一个或多个的正交频分复用（OFDM）信号，并且从一个或多个 的OFDM信号，尽管频率重叠。 具有该能力的接收机可以允许增加信道空间的有效带宽，因此可以允许更多设备同时共享信道空间。

公开(公告)号：US09116319B2

公开(公告)日：2015-08-25

申请号：US13086252

申请日：2011-04-13

Applicant: John Hongguang Zhang

Inventor： John Hongguang Zhang

IPC: G02B6/12 ,  G02B6/43 ,  G02B6/122 ,  G02B6/124 ,  G02B6/42 ,  G02B6/132 ,  G02B6/136

CPC classification number: G02B6/43 ,  G02B6/122 ,  G02B6/124 ,  G02B6/132 ,  G02B6/136 ,  G02B6/42 ,  G02B6/4214 ,  G02B2006/12102

Abstract: Disclosed is a photonic integrated circuit having a plurality of lenses and a method for making the same. The photonic integrated circuit is comprised of optical circuitry fabricated over an underlying circuitry layer. In some embodiments, the optical circuitry includes a dielectric material having recesses disposed within, layers of a light waveguide material deposited within the recesses, and lenses disposed over each layer of waveguide material. The underlying circuitry layer may include, for example, a semiconductor wafer as well as circuitry fabricated during front end of line (FEOL) semiconductor manufacturing such as, for example, sources, gates, drains, interconnects, contacts, resistors, and other circuitry that may be manufactured during FEOL processes. The underlying circuitry layer may also include circuitry manufactured during back end of line semiconductor manufacturing processes such as, for example, interconnect structures, metallization layers, and contacts.

Abstract translation: 公开了具有多个透镜的光子集成电路及其制造方法。 光子集成电路由在下面的电路层上制造的光学电路组成。 在一些实施例中，光学电路包括具有设置在沉积在凹部内的光波导材料的层内的凹陷的介电材料和设置在每层波导材料上的透镜。 底层电路层可以包括例如半导体晶片以及在前端（FEOL）半导体制造期间制造的电路，例如源，栅极，漏极，互连，触点，电阻器和其他电路，其中 可以在FEOL过程中制造。 底层电路层还可以包括在线半导体制造工艺的后端制造的电路，例如互连结构，金属化层和触点。

公开(公告)号：US20150228777A1

公开(公告)日：2015-08-13

申请号：US14175308

申请日：2014-02-07

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78684 ,  H01L29/78696

Abstract: Transistors having partially recessed gates are constructed on silicon-on-insulator (SOI) semiconductor wafers provided with a buried oxide layer (BOX), for example, FD-SOI and UTBB devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles. Formation of a partially recessed gate and raised epitaxial source and drain regions allow further improvements in transistor performance and reduction of short channel effects such as drain induced barrier lowering (DIBL) and control of a characteristic subthreshold slope. Gate recess can be varied to place the channel at different depths relative to the dopant profile, assisted by advanced process control. The partially recessed gate has an associated high-k gate dielectric that is initially formed in contact with three sides of the gate. Subsequent removal of the high-k sidewalls and substitution of a lower-k silicon nitride encapsulant lowers capacitance between the gate and the source and drain regions.

Abstract translation: 具有部分凹陷栅极的晶体管被​​构造在具有掩埋氧化物层（BOX）的例如FD-SOI和UTBB器件的绝缘体上硅（SOI）半导体晶片上。 外延生长的沟道区域放宽了掺杂源极和漏极配置图的限制。 部分凹入的栅极和升高的外延源极和漏极区域的形成允许晶体管性能的进一步改善和诸如漏极引起的栅极降低（DIBL）和特征亚阈值斜率的控制的短沟道效应的减少。 可以通过先进的过程控制辅助，改变栅极凹槽以使沟道相对于掺杂物分布形成不同的深度。 部分凹入的栅极具有最初形成为与栅极的三侧接触的相关联的高k栅极电介质。 随后去除高k侧壁和置换较低k氮化硅密封剂降低了栅极和源极和漏极区域之间的电容。

公开(公告)号：US09099570B2

公开(公告)日：2015-08-04

申请号：US14097556

申请日：2013-12-05

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare

IPC: H01L27/092 ,  H01L21/84 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L21/845 ,  H01L21/76205 ,  H01L21/76283 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795

Abstract: On a substrate formed of a first semiconductor material, a first overlying layer formed of a second semiconductor material is deposited. A second overlying layer formed of a third semiconductor material is deposited over the first overlying layer. The first and second overlying layers are patterned to define fins, wherein each fin includes a first region formed of the third material over a second region formed of the second material. An oxide material fills the space between the fins. A thermal oxidation is then performed to convert the second region to a material insulating the first region formed of the third material from the substrate. As an optional step, the second region formed of the second material is horizontally thinned before the oxide material is deposited and the thermal oxidation is performed. Once the fins are formed and insulated from the substrate, conventional FinFET fabrication is performed.

Abstract translation: 在由第一半导体材料形成的衬底上沉积由第二半导体材料形成的第一覆盖层。 由第三半导体材料形成的第二覆盖层沉积在第一覆盖层上。 图案化第一和第二覆盖层以限定翅片，其中每个翅片包括在由第二材料形成的第二区域上由第三材料形成的第一区域。 氧化物填充翅片之间的空间。 然后进行热氧化以将第二区域转换为将由第三材料形成的第一区域与衬底绝缘的材料。 作为可选步骤，在沉积氧化物材料并进行热氧化之前，由第二材料形成的第二区域被水平地薄化。 一旦翅片形成并与衬底绝缘，就进行常规的FinFET制造。

公开(公告)号：US09083573B2

公开(公告)日：2015-07-14

申请号：US13560928

申请日：2012-07-27

Applicant: Karthik Muralidhar ,  George A. Vlantis

Inventor： Karthik Muralidhar ,  George A. Vlantis

IPC: H04L27/00 ,  H04L25/02 ,  H04L25/03 ,  H04L27/26 ,  H04L27/12

CPC classification number: H04L25/022 ,  H04L25/0204 ,  H04L25/0224 ,  H04L25/03821 ,  H04L27/122 ,  H04L27/2601

Abstract: An embodiment of a transmitter includes detection, generating, and transmission stages. The detection stage is configured to detect a first signal having a first component that includes a frequency, and the generating stage is configured to generate a data component that includes approximately the frequency in response to the detection of the first signal. The transmission stage is configured to transmit a second signal having the data component while the detection stage is detecting the first signal. For example, two or more such transmitters (e.g., two or more smart phones) may simultaneously transmit OFDM signals on the same subcarrier frequencies and over the same channel space. By allowing the simultaneous transmission of multiple signals on the same frequencies and over the same channel space, such a transmitter may increase the effective bandwidth of the channel space, and thus may allow more devices to simultaneously share the same channel space.

Abstract translation: 发射机的实施例包括检测，产生和传输阶段。 检测级被配置为检测具有包括频率的第一分量的第一信号，并且生成级被配置为响应于第一信号的检测而生成包括大致频率的数据分量。 发送级被配置为在检测级检测到第一信号的同时发送具有数据分量的第二信号。 例如，两个或更多个这样的发射器（例如，两个或更多个智能电话）可以在相同的子载波频率上和相同的信道空间上同时发送OFDM信号。 通过允许在相同频率和相同信道空间上同时传输多个信号，这样的发射机可以增加信道空间的有效带宽，并且因此可以允许更多的设备同时共享相同的信道空间。

公开(公告)号：US09082625B2

公开(公告)日：2015-07-14

申请号：US14102873

申请日：2013-12-11

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Richard S. Wise ,  Yiheng Xu ,  John Zhang

IPC: B44C1/22 ,  H01L21/033 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L21/0337 ,  B81C1/0046 ,  G03F7/0002 ,  H01L21/31144

Abstract: Embodiments of present invention provide a method of forming device pattern. The method includes defining a device pattern to be created in a device layer; forming a sacrificial layer on top of the device layer; identifying an imprinting mold that, at a position along a height thereof, has a horizontal cross-sectional shape that represents the device pattern; pushing the imprinting mold uniformly into the sacrificial layer until at least the position of the imprinting mold reaches a level inside the sacrificial layer that is being pushed by the imprinting mold; removing the imprinting mold away from the sacrificial layer; forming a hard mask in recesses created by the imprinting mold in the sacrificial layer, the hard mask has a pattern representing the device pattern; and transferring the pattern of the hard mask into underneath the device layer.

Abstract translation: 本发明的实施例提供一种形成装置图案的方法。 该方法包括定义要在设备层中创建的设备图案; 在器件层的顶部上形成牺牲层; 识别在其高度的位置处具有表示装置图案的水平横截面形状的压印模具; 将压印模均匀地推入牺牲层，直到至少压印模具的位置达到被压印模推送的牺牲层内的水平面; 将所述压印模具远离所述牺牲层移除; 在由牺牲层中的压印模制成的凹部中形成硬掩模，硬掩模具有表示装置图案的图案; 并将硬掩模的图案转移到器件层的下方。

公开(公告)号：US09070709B2

公开(公告)日：2015-06-30

申请号：US14119395

申请日：2011-06-09

Applicant: Nicolas Posseme ,  Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Loubet ,  Maud Vinet

Inventor： Nicolas Posseme ,  Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Loubet ,  Maud Vinet

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/265

CPC classification number: H01L29/66477 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/84 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772

Abstract: The substrate successively includes a support substrate, an electrically insulating layer, a semiconductor material layer, and a gate pattern. The semiconductor material layer and gate pattern are covered by a covering layer. A first doping impurity is implanted in the semiconductor material layer through the covering layer so as to place the thickness of maximum concentration of the first doping impurity in the first layer. The covering layer is partly eliminated so as to form lateral spacers leaving source/drain electrodes free.

Abstract translation: 基板依次包括支撑基板，电绝缘层，半导体材料层和栅极图案。 半导体材料层和栅极图案被覆盖层覆盖。 第一掺杂杂质通过覆盖层注入到半导体材料层中，以将第一掺杂杂质的最大浓度的厚度置于第一层中。 覆盖层被部分地消除，以形成离开源极/漏电极的横向间隔物。

公开(公告)号：US20150162278A1

公开(公告)日：2015-06-11

申请号：US14098346

申请日：2013-12-05

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Hsueh-Chung Chen ,  Lawrence A. Clevenger ,  Yann Mignot ,  Carl Radens ,  Richard Stephen Wise ,  Yannick Loquet ,  Yiheng Xu

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53295 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates deep air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of a deep air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the deep air gap is used as an insulator and a means of reducing fringe capacitance between adjacent metal lines. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

Abstract translation: 在高性能集成电路中用作层间电介质的超低k电介质材料容易在结构上不稳定。 这种材料的杨氏模量降低，导致孔隙率，差的膜强度，开裂和空隙。 一种替代的双镶嵌互连结构将深空气隙结合到高模量介电材料中以维持结构稳定性，同时减小相邻纳米线之间的电容。 结合k = 1.0的深空气间隙补偿使用介电常数大于典型的超低k（ULK）介电值约2.2的介电常数的较高模量的膜。 使用含有深空气间隙的较高模量的膜作为绝缘体和减少相邻金属线之间的条纹电容的装置。 因此，两个相邻金属线之间的电介质层形成ULK /高模量介电双层。

公开(公告)号：US20150162194A1

公开(公告)日：2015-06-11

申请号：US14102873

申请日：2013-12-11

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Richard S. Wise ,  Yiheng Xu ,  John Zhang

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L21/0337 ,  B81C1/0046 ,  G03F7/0002 ,  H01L21/31144

Abstract: Embodiments of present invention provide a method of forming device pattern. The method includes defining a device pattern to be created in a device layer; forming a sacrificial layer on top of the device layer; identifying an imprinting mold that, at a position along a height thereof, has a horizontal cross-sectional shape that represents the device pattern; pushing the imprinting mold uniformly into the sacrificial layer until at least the position of the imprinting mold reaches a level inside the sacrificial layer that is being pushed by the imprinting mold; removing the imprinting mold away from the sacrificial layer; forming a hard mask in recesses created by the imprinting mold in the sacrificial layer, the hard mask has a pattern representing the device pattern; and transferring the pattern of the hard mask into underneath the device layer.

Abstract translation: 本发明的实施例提供一种形成装置图案的方法。 该方法包括定义要在设备层中创建的设备模式; 在器件层的顶部上形成牺牲层; 识别在其高度的位置处具有表示装置图案的水平横截面形状的压印模具; 将压印模均匀地推入牺牲层，直到至少压印模具的位置达到被压印模推送的牺牲层内的水平面; 将所述压印模具远离所述牺牲层移除; 在由牺牲层中的压印模制成的凹部中形成硬掩模，硬掩模具有表示装置图案的图案; 并将硬掩模的图案转移到器件层的下方。

公开(公告)号：US09039996B2

公开(公告)日：2015-05-26

申请号：US13272063

申请日：2011-10-12

Applicant: Massimiliano Pesaturo ,  Robert J. Powell

Inventor： Massimiliano Pesaturo ,  Robert J. Powell

IPC: B01L3/00 ,  C40B60/10

CPC classification number: B01L3/502707 ,  B01J2219/00317 ,  B01J2219/00466 ,  B01J2219/00702 ,  B01L3/502753 ,  B01L3/502761 ,  B01L2200/0668 ,  B01L2300/16 ,  B01L2300/161 ,  C40B60/10 ,  G01B5/00 ,  Y10T428/24355

Abstract: A micro device includes a substrate and a structure configured to bind to an object or a material, or not to bind to an object or material. The structure has a roughness based on a roughness of the object or material. For example, a microarray includes a substrate and a well positioned in the substrate and configured to bind to a type of bead. The well has a roughness based on a roughness of the type of bead to which the well is configured to bind. The roughness of the well is controlled by controlling a position and number of striations in the side of the well. In another example, a moveable component of a micro device may have a roughness different from a roughness of an adjacent component, to reduce the likelihood of the moveable component sticking to the adjacent component.

Abstract translation: 微型装置包括衬底和构造成结合物体或材料的结构，或不结合物体或材料。 该结构具有基于物体或材料的粗糙度的粗糙度。 例如，微阵列包括基底和定位在基底中并且被配置为结合一种珠粒的孔。 井具有基于井的类型的粗糙度的孔的粗糙度，孔被构造成结合。 井的粗糙度通过控制井的位置和条纹的数量来控制。 在另一示例中，微型装置的可移动部件可以具有与相邻部件的粗糙度不同的粗糙度，以减少可移动部件粘附到相邻部件的可能性。