公开(公告)号：US09218944B2

公开(公告)日：2015-12-22

申请号：US11589598

申请日：2006-10-30

Applicant: Madhavi R. Chandrachood ,  Michael N. Grimbergen ,  Khiem K. Nguyen ,  Richard Lewington ,  Ibrahim M. Ibrahim ,  Sheeba J. Panayil ,  Ajay Kumar

Inventor： Madhavi R. Chandrachood ,  Michael N. Grimbergen ,  Khiem K. Nguyen ,  Richard Lewington ,  Ibrahim M. Ibrahim ,  Sheeba J. Panayil ,  Ajay Kumar

IPC: H01J37/32 ,  H01L21/67 ,  H01L21/68 ,  C23C16/455 ,  C23C16/458 ,  C23C16/52 ,  H01L21/687

CPC classification number: H01J37/3211 ,  C23C16/45561 ,  C23C16/45563 ,  C23C16/4586 ,  C23C16/52 ,  H01J37/32449 ,  H01J37/32715 ,  H01J37/32935 ,  H01J37/32963 ,  H01J2237/334 ,  H01L21/67253 ,  H01L21/68785

Abstract: A plasma reactor has an array of passages extending through its workpiece support pedestal from a bottom thereof that forms a two-dimensional array of openings in the support surface. The reactor further includes a plurality of optical fibers, each fiber extending through a respective one of the passages. Optical sensing apparatus is coupled to the output ends of the optical fibers and is responsive in the range of wavelengths. The reactor further includes a tunable element capable of changing a two-dimensional etch rate distribution across the surface of a workpiece supported on the pedestal, and a process controller connected to receive information from the optical sensing apparatus and to transmit control commands to the tunable element.

Abstract translation: 等离子体反应器具有从其底部延伸穿过其工件支撑基座的通道阵列，其在支撑表面中形成开口的二维阵列。 反应器还包括多根光纤，每根光纤延伸通过相应的一个通道。 光学传感装置耦合到光纤的输出端并且在波长范围内是响应的。 反应器还包括能够改变穿过支撑在基座上的工件的表面上的二维蚀刻速率分布的可调谐元件，以及连接到从光学感测装置接收信息并将控制命令发送到可调元件的过程控制器 。

公开(公告)号：US20150255346A1

公开(公告)日：2015-09-10

申请号：US14200918

申请日：2014-03-07

Applicant: Jungrae PARK ,  Wei-Sheng LEI ,  James S. PAPANU ,  Brad EATON ,  Ajay KUMAR

Inventor： Jungrae PARK ,  Wei-Sheng LEI ,  James S. PAPANU ,  Brad EATON ,  Ajay KUMAR

IPC: H01L21/78 ,  B23K10/00 ,  B23K26/36

CPC classification number: H01L21/78 ,  B23K26/0823 ,  B23K26/0869 ,  B23K26/20 ,  B23K2101/001 ,  B23K2101/36 ,  B23K2103/166 ,  B23K2103/56

Abstract: Baking methods and tools for improved wafer coating are described. In one embodiment, a method of dicing a semiconductor wafer including integrated circuits involves coating a surface of the semiconductor wafer to form a mask covering the integrated circuits. The method involves baking the mask with radiation from one or more light sources. The method involves patterning the mask with a laser scribing process to provide a patterned mask with gaps, exposing regions of the substrate between the ICs. The method may also involves singulating the ICs, such as with a plasma etching operation.

Abstract translation: 描述了用于改进晶片涂层的烘烤方法和工具。 在一个实施例中，包括集成电路的半导体晶片的切割方法包括涂覆半导体晶片的表面以形成覆盖集成电路的掩模。 该方法包括用来自一个或多个光源的辐射来烘烤该掩模。 该方法包括用激光划线工艺对掩模进行图案化以提供具有间隙的图案化掩模，暴露在IC之间的衬底区域。 该方法还可以包括例如用等离子体蚀刻操作来分离IC。

公开(公告)号：US09112050B1

公开(公告)日：2015-08-18

申请号：US14276683

申请日：2014-05-13

Applicant: Wei-Sheng Lei ,  Prabhat Kumar ,  Brad Eaton ,  Ajay Kumar

Inventor： Wei-Sheng Lei ,  Prabhat Kumar ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/00 ,  H01L21/82 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/78

CPC classification number: H01L21/82 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/67069 ,  H01L21/67092 ,  H01L21/67109 ,  H01L21/67207 ,  H01L21/78

Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves introducing a substrate supported by a substrate carrier into a plasma etch chamber. The substrate has a patterned mask thereon covering integrated circuits and exposing streets of the substrate. The substrate carrier has a backside. The method also involves supporting at least a portion of the backside of the substrate carrier on a chuck of the plasma etch chamber. The method also involves cooling substantially all of the backside of the substrate carrier, the cooling involving cooling at least a first portion of the backside of the substrate carrier by the chuck. The method also involves plasma etching the substrate through the streets to singulate the integrated circuits while performing the cooling substantially all of the backside of the substrate carrier.

Abstract translation: 对具有多个集成电路的各晶片的切割半导体晶片的方法和装置进行说明。 在一个实例中，对具有多个集成电路的半导体晶片进行切割的方法包括将由衬底载体支撑的衬底引入等离子体蚀刻室。 衬底上具有图案化掩模，其覆盖集成电路并暴露衬底的街道。 衬底载体具有背面。 该方法还涉及将衬底载体的背侧的至少一部分支撑在等离子体蚀刻室的卡盘上。 该方法还包括冷却基板载体的基本上所有背面，冷却涉及通过卡盘冷却基板载体的背面的至少第一部分。 该方法还涉及通过街道等离子体蚀刻衬底以对集成电路进行单片化，同时基本上全部衬底载体的背面进行冷却。

公开(公告)号：US09108183B2

公开(公告)日：2015-08-18

申请号：US13457893

申请日：2012-04-27

Applicant: Ajay Kumar Dalai ,  Venkateswara Rao Surisetty

Inventor： Ajay Kumar Dalai ,  Venkateswara Rao Surisetty

IPC: C07C27/00 ,  B01J21/18 ,  B01J23/89 ,  B01J35/00 ,  B01J35/02 ,  B01J35/10 ,  B01J37/02 ,  B01J37/20 ,  C07C29/157 ,  C07C29/158 ,  B82Y30/00

CPC classification number: B01J21/185 ,  B01J23/8993 ,  B01J35/002 ,  B01J35/0066 ,  B01J35/023 ,  B01J35/1014 ,  B01J35/1038 ,  B01J35/1061 ,  B01J37/0205 ,  B01J37/0207 ,  B01J37/20 ,  B82Y30/00 ,  C07C29/157 ,  C07C29/158 ,  C07C31/08

Abstract: The present application includes alkali metal-promoted trimetallic catalysts for higher alcohol synthesis from synthesis gas, the catalyst comprising a catalyst of Formula (1): A-M1-M2-M3.

Abstract translation: 本申请包括用于由合成气合成高级醇的碱金属促进的金属催化剂，所述催化剂包含式（1）的催化剂：A-M1-M2-M3。

公开(公告)号：US20150214111A1

公开(公告)日：2015-07-30

申请号：US14590910

申请日：2015-01-06

Applicant: Wei-Sheng Lei ,  James S. Papanu ,  Prabhat Kumar ,  Brad Eaton ,  Ajay Kumar

Inventor： Wei-Sheng Lei ,  James S. Papanu ,  Prabhat Kumar ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/82 ,  H01L21/683 ,  H01L21/306 ,  H01L21/56

CPC classification number: H01L21/82 ,  H01L21/30604 ,  H01L21/561 ,  H01L21/67207 ,  H01L21/6836 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/743 ,  H01L2224/16145 ,  H01L2224/27001 ,  H01L2224/27436 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/83191 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Methods and systems for dicing a semiconductor wafer including a plurality of integrated circuits (ICs) are described. In one embodiment, a method involves adhering an adhesive tape to a thin water soluble dry film. The method involves applying the thin water soluble dry film adhered to the adhesive tape over a surface of the semiconductor wafer. The method involves removing the adhesive tape from the thin water soluble dry film. The thin water soluble dry film is patterned with a laser scribing process, exposing regions of the semiconductor wafer between the ICs. The method involves etching the semiconductor wafer through gaps in the patterned thin water soluble dry film, and removing the thin water soluble dry film.

Abstract translation: 描述了用于切割包括多个集成电路（IC）的半导体晶片的方法和系统。 在一个实施方案中，一种方法包括将粘合带粘附到薄水溶性干膜上。 该方法包括将粘附到粘合带上的薄水溶性干膜涂覆在半导体晶片的表面上。 该方法包括从薄水溶性干膜中去除粘合带。 用激光刻划工艺对薄水溶性干膜进行图案化，使IC之间的半导体晶片的区域暴露。 该方法包括通过图案化的薄水溶性干膜中的间隙蚀刻半导体晶片，以及去除薄水溶性干膜。

公开(公告)号：US20150200119A1

公开(公告)日：2015-07-16

申请号：US14671379

申请日：2015-03-27

Applicant: Brad EATON ,  Saravjeet SINGH ,  Wei-Sheng LEI ,  Madhava Rao YALAMANCHILI ,  Tong LIU ,  Ajay KUMAR

Inventor： Brad EATON ,  Saravjeet SINGH ,  Wei-Sheng LEI ,  Madhava Rao YALAMANCHILI ,  Tong LIU ,  Ajay KUMAR

IPC: H01L21/67 ,  H01J37/32 ,  B23K26/36 ,  B23K26/40 ,  H01L21/677 ,  H01L21/78

CPC classification number: H01L21/67161 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/50 ,  H01J37/32651 ,  H01J37/32788 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/67069 ,  H01L21/67115 ,  H01L21/67742 ,  H01L21/78 ,  Y10T29/5124

Abstract: In embodiments, a hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma etch is implemented for die singulation. The laser scribe process may be used to cleanly remove a mask layer, organic and inorganic dielectric layers, and device layers. The laser etch process may then be terminated upon exposure of, or partial etch of, the wafer or substrate. In embodiments, a multi-plasma etching approach is employed to dice the wafers where an isotropic etch is employed to improve the die sidewall following an anisotropic etch. The isotropic etch removes anisotropic etch byproducts, roughness, and/or scalloping from the anisotropically etched die sidewalls after die singulation.

Abstract translation: 在实施例中，实施涉及初始激光划片和随后的等离子体蚀刻的混合晶片或衬底切割工艺用于裸片切割。 激光划片工艺可用于清洁地去除掩模层，有机和无机介电层以及器件层。 然后可以在曝光或部分蚀刻晶片或衬底时终止激光蚀刻工艺。 在实施例中，采用多等离子体蚀刻方法来骰子晶片，其中采用各向同性蚀刻来改善各向异性蚀刻后的管芯侧壁。 各向同性蚀刻在单片切割之后从各向异性蚀刻的模具侧壁去除各向异性蚀刻副产物，粗糙度和/或扇贝。

公开(公告)号：US09041198B2

公开(公告)日：2015-05-26

申请号：US14060005

申请日：2013-10-22

Applicant: Wei-Sheng Lei ,  Brad Eaton ,  James S. Papanu ,  Ajay Kumar

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  James S. Papanu ,  Ajay Kumar

IPC: H01L23/34 ,  H01L21/78 ,  H01L21/3065 ,  B23K26/40

CPC classification number: H01L21/78 ,  B23K26/0006 ,  B23K26/0624 ,  B23K26/50 ,  B23K26/53 ,  B23K26/57 ,  B23K2101/40 ,  B23K2103/56 ,  H01L21/3065 ,  H01L21/82

Abstract: Maskless hybrid laser scribing and plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer having a front surface with a plurality of integrated circuits thereon and having a passivation layer disposed between and covering metal pillar/solder bump pairs of the integrated circuits involves laser scribing, without the use of a mask layer, the passivation layer to provide scribe lines exposing the semiconductor wafer. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, wherein the passivation layer protects the integrated circuits during at least a portion of the plasma etching. The method also involves thinning the passivation layer to partially expose the metal pillar/solder bump pairs of the integrated circuits.

Abstract translation: 描述了无掩模混合激光划线和等离子体蚀刻晶片切割工艺。 在一个示例中，将具有其上具有多个集成电路的前表面的半导体晶片切割并且具有设置在其上并且覆盖集成电路的金属柱/焊料凸块对之间的钝化层的方法包括激光划线，而不使用 掩模层，钝化层以提供暴露半导体晶片的划线。 该方法还包括通过划线等离子体蚀刻半导体晶片以对集成电路进行分离，其中钝化层在等离子体蚀刻的至少一部分期间保护集成电路。 该方法还涉及使钝化层变薄以部分地暴露集成电路的金属柱/焊料凸块对。

公开(公告)号：US20150111364A1

公开(公告)日：2015-04-23

申请号：US14454656

申请日：2014-08-07

Applicant: Wei-Sheng Lei ,  Brad Eaton ,  James S. Papanu ,  Ajay Kumar

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  James S. Papanu ,  Ajay Kumar

IPC: H01L21/82 ,  H01L21/3065

CPC classification number: H01L21/78 ,  B23K26/0006 ,  B23K26/0624 ,  B23K26/50 ,  B23K26/53 ,  B23K26/57 ,  B23K2101/40 ,  B23K2103/56 ,  H01L21/3065 ,  H01L21/82

Abstract: Maskless hybrid laser scribing and plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer having a front surface with a plurality of integrated circuits thereon and having a passivation layer disposed between and covering metal pillar/solder bump pairs of the integrated circuits involves laser scribing, without the use of a mask layer, the passivation layer to provide scribe lines exposing the semiconductor wafer. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, wherein the passivation layer protects the integrated circuits during at least a portion of the plasma etching. The method also involves thinning the passivation layer to partially expose the metal pillar/solder bump pairs of the integrated circuits.

Abstract translation: 描述了无掩模混合激光划线和等离子体蚀刻晶片切割工艺。 在一个示例中，将具有其上具有多个集成电路的前表面的半导体晶片切割并且具有设置在其上并且覆盖集成电路的金属柱/焊料凸块对之间的钝化层的方法包括激光划线，而不使用 掩模层，钝化层以提供暴露半导体晶片的划线。 该方法还包括通过划线等离子体蚀刻半导体晶片以对集成电路进行分离，其中钝化层在等离子体蚀刻的至少一部分期间保护集成电路。 该方法还涉及使钝化层变薄以部分地暴露集成电路的金属柱/焊料凸块对。

公开(公告)号：US08975163B1

公开(公告)日：2015-03-10

申请号：US14249891

申请日：2014-04-10

Applicant: Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

Inventor： Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/46 ,  H01L21/78 ,  H01L23/544

CPC classification number: H01L21/78 ,  H01L21/6836 ,  H01L2221/68318 ,  H01L2221/68327

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer comprising a plurality of integrated circuits involves forming a mask above the semiconductor wafer. The mask includes a layer covering and protecting the integrated circuits. The semiconductor wafer has a thickness. The method also involves laser scribing the mask and a majority of the thickness of the semiconductor wafer to provide scribe lines in the mask and the semiconductor wafer. The scribe lines are formed between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits.

Abstract translation: 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个示例中，包括多个集成电路的半导体晶片的切割方法包括在半导体晶片上形成掩模。 掩模包括覆盖并保护集成电路的层。 半导体晶片具有厚度。 该方法还包括激光划线掩模和半导体晶片的大部分厚度，以在掩模和半导体晶片中提供划线。 划线在集成电路之间形成。 该方法还涉及通过划线等离子体蚀刻半导体晶片以对集成电路进行分离。

公开(公告)号：US20150037915A1

公开(公告)日：2015-02-05

申请号：US14035402

申请日：2013-09-24

Applicant: Wei-Sheng LEI ,  Brad Eaton ,  Apama IYER ,  Madhava Rao Yalamanchili ,  Ajay Kumar

Inventor： Wei-Sheng LEI ,  Brad Eaton ,  Apama IYER ,  Madhava Rao Yalamanchili ,  Ajay Kumar

IPC: H01L21/78 ,  B23K26/03 ,  B23K26/04 ,  B23K26/06

CPC classification number: H01L21/78 ,  B23K26/032 ,  B23K26/046 ,  B23K26/0624 ,  B23K26/0661 ,  B23K26/40 ,  B23K2103/172 ,  B23K2103/42 ,  B23K2103/50

Abstract: In embodiments, a method of laser scribing a mask disposed over a semiconductor wafer includes determining a height of the semiconductor over which a mask layer is disposed prior to laser scribing the mask layer. In one embodiment the method includes: determining a height of the semiconductor wafer under the mask in a dicing street using an optical sensor and patterning the mask with a laser scribing process. The laser scribing process focuses a scribing laser beam at a plane corresponding to the determined height of the semiconductor wafer in the dicing street. Examples of determining the height of the semiconductor wafer can include directing a laser beam to the dicing street of the semiconductor wafer, which is transmitted through the mask and reflected from the wafer, and identifying an image on a surface of the wafer under the mask with a camera.

Abstract translation: 在实施例中，激光划片设置在半导体晶片上方的掩模的方法包括确定在激光划线掩模层之前在其上设置掩模层的半导体的高度。 在一个实施例中，该方法包括：使用光学传感器在切割街道中确定半导体晶片下面的高度，并用激光划线工艺对掩模进行构图。 激光划线工艺将划线激光束聚焦在与切割街道中确定的半导体晶片的高度相对应的平面上。 确定半导体晶片的高度的示例可以包括将激光束引导到半导体晶片的切割街道，透射通过掩模并从晶片反射，并且在掩模下面在晶片的表面上识别图像， 相机。