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    UV-CURE PRE-TREATMENT OF CARRIER FILM FOR WAFER DICING USING HYBRID LASER SCRIBING AND PLASMA ETCH APPROACH
    1.
    发明申请
    UV-CURE PRE-TREATMENT OF CARRIER FILM FOR WAFER DICING USING HYBRID LASER SCRIBING AND PLASMA ETCH APPROACH 有权
    使用混合激光扫描和等离子体蚀刻方法进行波长涂覆的载体膜的UV固化预处理

    公开(公告)号：US20160315009A1

    公开(公告)日：2016-10-27

    申请号：US14697391

    申请日：2015-04-27

    申请人： Wei-Sheng Lei ,  Brad Eaton ,  Jungrae Park ,  Ajay Kumar ,  James S. Papanu ,  Prabhat Kumar

    发明人： Wei-Sheng Lei ,  Brad Eaton ,  Jungrae Park ,  Ajay Kumar ,  James S. Papanu ,  Prabhat Kumar

    IPC分类号： H01L21/78 ,  H01L21/683 ,  H01L21/268 ,  H01L21/67 ,  H01L21/308 ,  H01L21/3065

    CPC分类号： H01L21/78 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/67069 ,  H01L21/67207 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

    摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits on a front side of the semiconductor wafer includes adhering a back side the semiconductor wafer on the dicing tape of a substrate carrier. Subsequent to adhering the semiconductor wafer on a dicing tape, the dicing tape is treated with a UV-cure process. Subsequent to treating the dicing tape with the UV-cure process, a dicing mask is formed on the front side of the semiconductor wafer, the dicing mask covering and protecting the integrated circuits. The dicing mask is patterned with a laser scribing process to provide gaps in the dicing mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the dicing mask layer to singulate the integrated circuits.

    摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个示例中，在半导体晶片的正面上切割具有多个集成电路的半导体晶片的方法包括将半导体晶片的背面粘附在基板载体的切割带上。 在将半导体晶片粘附在切割带上之后，用UV固化工艺处理切割带。 在通过UV固化处理处理切割带之后，在半导体晶片的前侧形成切割掩模，该切割掩模覆盖并保护集成电路。 用激光刻划工艺对切割掩模进行图案化，以在切割掩模之间提供间隙，在半导体晶片的间隙暴露在集成电路之间。 通过切割掩模层中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

    Vacuum lamination of polymeric dry films for wafer dicing using hybrid laser scribing and plasma etch approach
    2.
    发明授权
    Vacuum lamination of polymeric dry films for wafer dicing using hybrid laser scribing and plasma etch approach 有权
    使用混合激光划线和等离子体蚀刻方法对用于晶片切割的聚合物干膜进行真空层压

    公开(公告)号：US09159624B1

    公开(公告)日：2015-10-13

    申请号：US14589913

    申请日：2015-01-05

    申请人： Wei-Sheng Lei ,  Prabhat Kumar ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

    发明人： Wei-Sheng Lei ,  Prabhat Kumar ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

    IPC分类号： H01L21/78 ,  H01L21/8234

    CPC分类号： H01L21/78 ,  H01L21/6836 ,  H01L21/8234 ,  H01L2221/68327 ,  H01L2221/6834

    摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves laminating a polymeric mask layer onto a front side of the semiconductor wafer by dry film vacuum lamination, the polymeric mask layer covering and protecting the integrated circuits. The method also involves patterning the polymeric mask layer with a laser scribing process to provide gaps in the polymeric mask layer, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the gaps in the polymeric mask layer to singulate the integrated circuits. The method also involves, subsequent to plasma etching the semiconductor wafer, removing the polymeric mask layer.

    摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个实例中，对具有多个集成电路的半导体晶片进行切割的方法包括通过干膜真空层压将聚合物掩模层层压到半导体晶片的正面上，该聚合物掩模层覆盖并保护集成电路。 该方法还包括用激光划线工艺图案化聚合物掩模层，以在聚合物掩模层中提供间隙，间隙暴露集成电路之间的半导体晶片的区域。 该方法还包括通过聚合物掩模层中的间隙等离子体蚀刻半导体晶片以对集成电路进行分离。 该方法还涉及在等离子体蚀刻半导体晶片之后，去除聚合物掩模层。

    Residue removal from singulated die sidewall
    4.
    发明授权
    Residue removal from singulated die sidewall 有权
    从单个模具侧壁残留除去

    公开(公告)号：US09076860B1

    公开(公告)日：2015-07-07

    申请号：US14248165

    申请日：2014-04-08

    申请人： Wei-Sheng Lei ,  Prabhat Kumar ,  James S. Papanu ,  Ajay Kumar ,  Brad Eaton

    发明人： Wei-Sheng Lei ,  Prabhat Kumar ,  James S. Papanu ,  Ajay Kumar ,  Brad Eaton

    IPC分类号： H01L21/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/67

    CPC分类号： H01L21/02076 ,  H01L21/67092 ,  H01L21/67207

    摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The method also involves patterning the mask with a laser scribing process to provide gaps in the mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the gaps in the mask to singulate the integrated circuits. The method also involves, subsequent to plasma etching the semiconductor wafer, removing etch residue from sidewalls of the singulated integrated circuits.

    摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个示例中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模包括覆盖并保护集成电路的层。 该方法还包括用激光划线工艺对掩模进行图案化以在掩模中提供间隙，在半导体晶片的间隙暴露集成电路之间的半导体晶片。 该方法还包括通过掩模中的间隙等离子体蚀刻半导体晶片以对集成电路进行分离。 该方法还涉及在等离子体蚀刻半导体晶片之后，从单个集成电路的侧壁去除蚀刻残留物。

    IMPROVED WAFER COATING
    7.
    发明申请
    IMPROVED WAFER COATING 审中-公开
    改进的涂层

    公开(公告)号：US20150221505A1

    公开(公告)日：2015-08-06

    申请号：US14658102

    申请日：2015-03-13

    申请人： Jungrae Park ,  Wei-Sheng Lei ,  Prabhat Kumar ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

    发明人： Jungrae Park ,  Wei-Sheng Lei ,  Prabhat Kumar ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

    IPC分类号： H01L21/02 ,  H01L21/683 ,  H01L21/308 ,  B05B3/10 ,  B05B1/00

    CPC分类号： H01L21/02282 ,  B05B1/00 ,  B05B3/1014 ,  B05B3/1035 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/6715 ,  H01L21/6835 ,  H01L21/78 ,  H01L2221/68327

    摘要： Improved wafer coating processes, apparatuses, and systems are described. In one embodiment, an improved spin-coating process and system is used to form a mask for dicing a semiconductor wafer with a laser plasma dicing process. In one embodiment, a spin-coating apparatus for forming a film over a semiconductor wafer includes a rotatable stage configured to support the semiconductor wafer. The rotatable stage has a downward sloping region positioned beyond a perimeter of the semiconductor wafer. The apparatus includes a nozzle positioned above the rotatable stage and configured to dispense a liquid over the semiconductor wafer. The apparatus also includes a motor configured to rotate the rotatable stage.

    摘要翻译： 描述了改进的晶片涂布工艺，装置和系统。 在一个实施例中，改进的旋涂工艺和系统用于形成用激光等离子体切割工艺切割半导体晶片的掩模。 在一个实施例中，用于在半导体晶片上形成膜的旋涂装置包括被配置为支撑半导体晶片的可旋转台。 可旋转台具有位于半导体晶片周边之外的向下倾斜区域。 该设备包括位于可旋转台上方并被配置为在半导体晶片上分配液体的喷嘴。 该装置还包括构造成旋转可旋转台的马达。

    Wafer dicing using hybrid laser scribing and plasma etch approach with mask application by vacuum lamination
    9.
    发明授权
    Wafer dicing using hybrid laser scribing and plasma etch approach with mask application by vacuum lamination 有权
    使用混合激光划线和等离子体蚀刻方法的薄片切割，通过真空层压法进行掩模应用

    公开(公告)号：US09142459B1

    公开(公告)日：2015-09-22

    申请号：US14320426

    申请日：2014-06-30

    申请人： Prabhat Kumar ,  Wei-Sheng Lei ,  Brad Eaton ,  Ajay Kumar

    发明人： Prabhat Kumar ,  Wei-Sheng Lei ,  Brad Eaton ,  Ajay Kumar

    IPC分类号： H01L21/00 ,  H01L21/822 ,  H01L21/033 ,  H01L21/02

    CPC分类号： H01L21/0337 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/78

    摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves applying an adhesive layer to a front side of the semiconductor wafer. A mask layer is laminated onto the front side of the semiconductor wafer, the mask layer covering and protecting the integrated circuits. The adhesive layer adheres the mask layer to the front side of the semiconductor wafer. The mask layer is patterned with a laser scribing process to provide gaps in the mask layer, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the mask layer to singulate the integrated circuits.

    摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个示例中，对具有多个集成电路的半导体晶片进行切割的方法包括将粘合剂层施加到半导体晶片的正面。 掩模层被层叠在半导体晶片的前侧，掩模层覆盖并保护集成电路。 粘合剂层将掩模层粘附到半导体晶片的正面。 通过激光划线工艺对掩模层进行构图，以在掩模层中提供间隙，在半导体晶片的间隙暴露在集成电路之间。 通过掩模层中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

    Hybrid dicing process using a blade and laser
    10.
    发明授权
    Hybrid dicing process using a blade and laser 有权
    使用刀片和激光的混合切割工艺

    公开(公告)号：US09130057B1

    公开(公告)日：2015-09-08

    申请号：US14320405

    申请日：2014-06-30

    申请人： Prabhat Kumar ,  Wei-Sheng Lei ,  James Papanu ,  Brad Eaton ,  Ajay Kumar

    发明人： Prabhat Kumar ,  Wei-Sheng Lei ,  James Papanu ,  Brad Eaton ,  Ajay Kumar

    IPC分类号： H01L21/822 ,  H01L21/67 ,  B23K26/00 ,  B26D9/00

    CPC分类号： B26D9/00 ,  B23K26/0624 ,  B23K26/53 ,  B23K2101/40 ,  B23K2103/172 ,  B23K2103/50 ,  B23K2103/54 ,  B26D3/06 ,  B28D5/022 ,  H01L21/67092 ,  H01L21/78

    摘要： A method and system of hybrid dicing using a blade and laser are described. In one embodiment, a method involves focusing a laser beam inside the substrate in regions between the integrated circuits, inducing defects inside the substrate in the regions. The method also involves forming a groove on a surface of the substrate with a blade saw in the regions. The method further involves singulating the integrated circuits at the regions with the induced defects and the groove. In one embodiment, a system includes a laser module configured to focus a laser beam inside the substrate in regions between the integrated circuits, inducing defects inside the substrate in the regions. A blade grooving module is configured to form a groove in a surface of the substrate with a blade saw in the regions.

    摘要翻译： 描述了使用刀片和激光器的混合切割的方法和系统。 在一个实施例中，一种方法包括将集成电路之间的区域内的激光束聚焦在衬底内，从而在区域内的衬底内引起缺陷。 该方法还涉及在该区域中具有刀片锯的基板的表面上形成凹槽。 该方法还涉及在具有感应缺陷和凹槽的区域处分离集成电路。 在一个实施例中，系统包括激光模块，该激光模块被配置为将集成电路之间的区域内的激光束聚焦在衬底内，从而在该区域内的衬底内引起缺陷。 刀片切槽模块被配置为在所述区域中具有刀片锯的基板的表面中形成凹槽。