公开(公告)号：US20100227479A1

公开(公告)日：2010-09-09

申请号：US12660793

申请日：2010-03-04

Applicant: Sunjung Kim ,  JongCheol Lee ,  Bonyoung Koo ,  Wansik Hwang ,  Joon Gon Lee ,  JungHyeon Kim

Inventor： Sunjung Kim ,  JongCheol Lee ,  Bonyoung Koo ,  Wansik Hwang ,  Joon Gon Lee ,  JungHyeon Kim

IPC: H01L21/3105

CPC classification number: H01L21/3143 ,  H01L21/02175 ,  H01L21/022 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/788 ,  H01L29/792

Abstract: Provided are a semiconductor device and a method of fabricating the same. The method includes forming a metal nitride layer and a metal oxide layer on a semiconductor substrate to be in contact with each other, and annealing the substrate including the metal nitride layer and the metal oxide layer to form a metal oxynitride layer.

Abstract translation: 提供半导体器件及其制造方法。 该方法包括在半导体衬底上形成金属氮化物层和金属氧化物层以彼此接触，并且使包括金属氮化物层和金属氧化物层的衬底退火以形成金属氧氮化物层。

公开(公告)号：US20160300929A1

公开(公告)日：2016-10-13

申请号：US15062742

申请日：2016-03-07

Applicant: JINBUM KIM ,  Jaeyoung Park ,  Donghun Lee ,  Jeongho Yoo ,  Jieon Yoon ,  Kwan Heum Lee ,  Choeun Lee ,  Bonyoung Koo

Inventor： JINBUM KIM ,  Jaeyoung Park ,  Donghun Lee ,  Jeongho Yoo ,  Jieon Yoon ,  Kwan Heum Lee ,  Choeun Lee ,  Bonyoung Koo

IPC: H01L29/66 ,  H01L29/12 ,  H01L21/30 ,  H01L29/423 ,  H01L29/40 ,  H01L29/04 ,  H01L29/417

CPC classification number: H01L29/66636 ,  H01L21/3003 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/12 ,  H01L29/165 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/78

Abstract: A method of fabricating a semiconductor device is provided as follows. A source/drain pattern is formed on a substrate. The source/drain pattern contains silicon atoms and germanium atoms. At least one germanium atom is removed from the germanium atoms of the source/drain pattern.

Abstract translation: 如下提供制造半导体器件的方法。 在衬底上形成源极/漏极图案。 源/漏模式包含硅原子和锗原子。 从源极/漏极图案的锗原子中去除至少一个锗原子。

公开(公告)号：US09466721B1

公开(公告)日：2016-10-11

申请号：US14978155

申请日：2015-12-22

Applicant: Jinbum Kim ,  Kwanheum Lee ,  Hyunjae Kang ,  Bonyoung Koo ,  Seokhoon Kim ,  Kanghun Moon ,  Jaeyoung Park ,  Byeongchan Lee ,  Sunyoung Lee ,  Choeun Lee ,  Hanki Lee ,  Sujin Jung ,  Yang Xu

Inventor： Jinbum Kim ,  Kwanheum Lee ,  Hyunjae Kang ,  Bonyoung Koo ,  Seokhoon Kim ,  Kanghun Moon ,  Jaeyoung Park ,  Byeongchan Lee ,  Sunyoung Lee ,  Choeun Lee ,  Hanki Lee ,  Sujin Jung ,  Yang Xu

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/785 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/42364 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device may include a fin active region including a lower fin active region surrounded by a device isolation layer and an upper fin active region protruding from a top surface of the device isolation layer, a gate pattern disposed on top and side surfaces of the upper fin active region, and a source/drain region formed in the fin active region located at a side of the gate pattern. The gate pattern extends onto the device isolation region. The source/drain region includes a trench and epitaxial layers that fill the trench. Sidewalls of the trench include first sidewalls and second sidewalls that connect the first sidewalls to a bottom surface of the trench. The bottom surface of the trench is located at a lower level than the top surface of the device isolation layer beneath the gate pattern, and the second sidewalls of the trench have inclined {111} planes.

Abstract translation: 半导体器件可以包括鳍状物活性区域，其包括被器件隔离层包围的下部翅片有源区域和从器件隔离层的顶表面突出的上部翅片有源区域，设置在上部的顶部和侧面上的栅极图案 鳍状物活性区域和形成在位于栅极图案侧的鳍状物活性区域中的源极/漏极区域。 栅极图案延伸到器件隔离区域上。 源/漏区包括填充沟槽的沟槽和外延层。 沟槽的侧壁包括将第一侧壁连接到沟槽的底表面的第一侧壁和第二侧壁。 沟槽的底表面位于比栅极图案下方的器件隔离层的顶表面更低的水平处，并且沟槽的第二侧壁具有倾斜的{111}平面。

公开(公告)号：US20150348982A1

公开(公告)日：2015-12-03

申请号：US14819841

申请日：2015-08-06

Applicant: Jeeyong Kim ,  Woonkyung LEE ,  Sunggil KIM ,  Jin-Kyu KANG ,  Jung-Hwan LEE ,  Bonyoung KOO ,  Kihyun HWANG ,  Byoungsun JU ,  Jintae NOH

Inventor： Jeeyong Kim ,  Woonkyung LEE ,  Sunggil KIM ,  Jin-Kyu KANG ,  Jung-Hwan LEE ,  Bonyoung KOO ,  Kihyun HWANG ,  Byoungsun JU ,  Jintae NOH

IPC: H01L27/115 ,  H01L29/78 ,  H01L23/535

CPC classification number: H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

公开(公告)号：US08319276B2

公开(公告)日：2012-11-27

申请号：US12712366

申请日：2010-02-25

Applicant: Toshiro Nakanishi ,  Chanjin Park ,  Siyoung Choi ,  Bonyoung Koo

Inventor： Toshiro Nakanishi ,  Chanjin Park ,  Siyoung Choi ,  Bonyoung Koo

IPC: H01L29/792

CPC classification number: H01L21/28282 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/66833 ,  H01L29/792

Abstract: A non-volatile memory device includes: word line disposed on a substrate; an active region crossing over the word line; and a charge trap layer that is between the word line and the active region.

Abstract translation: 一种非易失性存储装置，包括：设置在基板上的字线; 跨越字线的活跃区域; 以及位于字线和有源区之间的电荷陷阱层。

公开(公告)号：US20100252877A1

公开(公告)日：2010-10-07

申请号：US12712366

申请日：2010-02-25

Applicant: Toshiro Nakanishi ,  Chanjin Park ,  Siyoung Choi ,  Bonyoung Koo

Inventor： Toshiro Nakanishi ,  Chanjin Park ,  Siyoung Choi ,  Bonyoung Koo

IPC: H01L29/792

CPC classification number: H01L21/28282 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/66833 ,  H01L29/792

Abstract: A non-volatile memory device includes: word line disposed on a substrate; an active region crossing over the word line; and a charge trap layer that is between the word line and the active region.

Abstract translation: 一种非易失性存储装置，包括：设置在基板上的字线; 跨越字线的活跃区域; 以及位于字线和有源区之间的电荷陷阱层。

公开(公告)号：US20160293763A1

公开(公告)日：2016-10-06

申请号：US14989956

申请日：2016-01-07

Applicant: Dongwoo KIM ,  Seung Hun LEE ,  Sunjung KIM ,  Hyun Jung LEE ,  Bonyoung KOO

Inventor： Dongwoo KIM ,  Seung Hun LEE ,  Sunjung KIM ,  Hyun Jung LEE ,  Bonyoung KOO

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L29/7849 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/785

Abstract: A semiconductor device includes a buffer layer on a substrate, the buffer layer having a lattice constant different from that of the substrate, a fin structure upwardly protruding from the buffer layer, a gate electrode crossing over the fin structure, a cladding layer at a side of the fin structure and covering a top surface and sidewalls of the fin structure, and an interfacial layer between the cladding layer and the fin structure, the interfacial layer including a same element as the buffer layer.

Abstract translation: 半导体器件包括衬底上的缓冲层，缓冲层具有不同于衬底的晶格常数，从缓冲层向上突出的鳍结构，在鳍结构上交叉的栅电极，侧面的覆层 的翅片结构并且覆盖翅片结构的顶表面和侧壁，以及覆盖层和鳍结构之间的界面层，界面层包括与缓冲层相同的元件。

公开(公告)号：US20150147861A1

公开(公告)日：2015-05-28

申请号：US14543820

申请日：2014-11-17

Applicant: JAEYOUNG PARK ,  SUNGHO KANG ,  KICHUL KIM ,  Sunyoung LEE ,  HAN KI LEE ,  BONYOUNG KOO

Inventor： JAEYOUNG PARK ,  SUNGHO KANG ,  KICHUL KIM ,  Sunyoung LEE ,  HAN KI LEE ,  BONYOUNG KOO

IPC: H01L21/3065 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/0206 ,  H01L21/302 ,  H01L21/306 ,  H01L21/32053 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/34 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method of manufacturing a semiconductor device includes forming a first plurality of recessed regions in a substrate, the substrate having a protruded active region between the first plurality of recessed regions and the protruded active region having an upper surface and a sidewall, forming a device isolation film in the first plurality of recessed regions, the device isolation film exposing the upper surface and an upper portion of the sidewall of the protruded active region, and performing a first plasma treatment on the exposed surface of the protruded active region, wherein the plasma treatment is performed using a plasma gas containing at least one of an inert gas and a hydrogen gas in a temperature of less than or equal to about 700.

Abstract translation: 一种制造半导体器件的方法包括在衬底中形成第一多个凹陷区域，所述衬底在所述第一多个凹陷区域之间具有突出的有源区域和所述突出的有源区域具有上表面和侧壁，形成器件隔离 在所述第一多个凹陷区域中的膜，所述器件隔离膜暴露所述突出的有源区的所述上表面和所述侧壁的上部，并且对所述突出的有源区的所述暴露表面进行第一等离子体处理，其中所述等离子体处理 使用包含惰性气体和氢气中的至少一种的等离子体气体在小于或等于约700℃的温度下进行。

公开(公告)号：US20150145018A1

公开(公告)日：2015-05-28

申请号：US14568737

申请日：2014-12-12

Applicant: Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

Inventor： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

IPC: H01L29/49 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

Abstract translation: 提供半导体器件和制造半导体器件的方法。 半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。 第一浓度可能高于第二浓度。